MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 49

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1. The Port E output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. For
2. CAN functionality is not available on the MC9S12GC Family members.
1.3.3
Not Bonded Pins:
Freescale Semiconductor
Function 1
Pin Name
example, in special test mode RDWE = LSTRE = 1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer
to S12_MEBI user guide for PEAR register details.
PP[2:0]
PS[3:2]
PJ[7:6]
PT[7:5]
PT[4:0]
PM5
PM4
PM3
PM2
PM1
PM0
PS1
PS0
If the port pins are not bonded out in the chosen package the user should initialize the registers to
be inputs with enabled pull resistance to avoid excess current consumption. This applies to the
following pins:
(48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port
J[7:6], PortS[3:2]
(52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port
J[7:6], PortS[3:2]
Pin Initialization for 48- and 52-Pin LQFP Bond Out Versions
Function 2
Pin Name
KWP[2:0]
KWJ[7:6]
IOC[7:5]
IOC[4:0]
RXCAN
TXCAN
MOSI
MISO
SCK
RXD
TXD
SS
—
Function 3
Pin Name
PW[2:0]
PW[4:0]
—
—
—
—
—
—
—
—
—
—
—
Table 1-5. Signal Properties (continued)
MC9S12C-Family / MC9S12GC-Family
Domain
Power
V
V
V
V
V
V
V
V
V
V
V
V
V
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
PERM/
PERM/
PERM/
PERM/
PERM/
PERM/
PERP/
PERS/
PERS/
PERS/
PERT/
PERT/
PERJ/
PPSM
PPSM
PPSM
PPSM
PPSM
PPSM
CTRL
PPSP
PPSS
PPSS
PPSS
PPST
PPST
PPSJ
Rev 01.24
Internal Pull
Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
Resistor
Disabled
Disabled
Disabled
Disabled
Reset
State
Up
Up
Up
Up
Up
Up
Up
Up
Up
Port P I/O pins, keypad wake-up, PWM outputs
Port J I/O pins and keypad wake-up
Port M I/O pin and SPI SCK signal
Port M I/O pin and SPI MOSI signal
Port M I/O pin and SPI SS signal
Port M I/O pin and SPI MISO signal
Port M I/O pin and CAN transmit signal
Port M I/O pin and CAN receive signal
Port S I/O pins
Port S I/O pin and SCI transmit signal
Port S I/O pin and SCI receive signal
Port T I/O pins shared with timer (TIM)
Port T I/O pins shared with timer and PWM
Description
2
(2)
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