MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 149

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.3.2.15
Read: Anytime
Write: Anytime
This port is associated with the internal memory expansion emulation pins. When the port is not enabled
to emulate the internal memory expansion, the port pins are used as general-purpose I/O. When port K is
operating as a general-purpose I/O port, DDRK determines the primary direction for each port K pin. A 1
causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impedance
input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTK register.
If the DDR bit is 0 (input) the buffered pin input is read. If the DDR bit is 1 (output) the output of the port
data register is read.
This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE
register is set. Therefore, these accesses will be echoed externally.
When inputs, these pins can be selected to be high impedance or pulled up, based upon the state of the
PUPKE bit in the PUCR register.
Freescale Semiconductor
Module Base + 0x0032
Starting address location affected by INITRG register setting.
Pin Function
Port K, Bits 5:0
Port K, Bit 7
Port K, Bit 6
Alternate
Field
5:0
Reset
7
6
W
R
Port K Data Register (PORTK)
Port K, Bit 7 — This bit is used as an emulation chip select signal for the emulation of the internal memory
expansion, or as general-purpose I/O, depending upon the state of the EMK bit in the MODE register. While
this bit is used as a chip select, the external bit will return to its de-asserted state (V
cycle just after the negative edge of ECLK, unless the external access is stretched and ECLK is free-running
(ESTR bit in EBICTL = 0). See the MMC block description chapter for additional details on when this signal
will be active.
Port K, Bit 6 — This bit is used as an external chip select signal for most external accesses that are not
selected by ECS (see the MMC block description chapter for more details), depending upon the state the of
the EMK bit in the MODE register. While this bit is used as a chip select, the external pin will return to its de-
asserted state (V
access is stretched and ECLK is free-running (ESTR bit in EBICTL = 0).
Port K, Bits 5:0 — These six bits are used to determine which FLASH/ROM or external memory array page
is being accessed. They can be viewed as expanded addresses XAB19–XAB14 of the 20-bit address used to
access up to1M byte internal FLASH/ROM or external memory array. Alternatively, these bits can be used for
general-purpose I/O depending upon the state of the EMK bit in the MODE register.
Bit 7
ECS
0
7
XCS
6
0
6
DD
) for approximately 1/4 cycle just after the negative edge of ECLK, unless the external
Figure 4-19. Port K Data Register (PORTK)
Table 4-13. PORTK Field Descriptions
MC9S12C-Family / MC9S12GC-Family
XAB19
5
0
5
Rev 01.24
XAB18
4
0
4
Description
XAB17
Chapter 4 Multiplexed External Bus Interface (MEBIV3)
3
3
0
XAB16
2
2
0
DD
XAB15
) for approximately 1/4
1
0
1
XAB14
Bit 0
0
0
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