MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 280

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
If the MCU gets an external reset during pseudo-stop mode active, the CRG asynchronously restores all
configuration bits in the register space to its default settings and starts the reset generator. After completing
the reset sequence processing begins by fetching the normal reset vector. Pseudo-stop mode is exited and
the MCU is in run mode again.
If the clock monitor is enabled (CME = 1) the MCU is able to leave pseudo-stop mode when loss of
oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG
generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same
compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the
SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE=1). After generating the
interrupt the CRG enters self-clock mode and starts the clock quality checker (see
Section 9.4.4, “Clock
Quality
Checker”). Then the MCU continues with normal operation. If the SCM interrupt is blocked by
SCMIE = 0, the SCMIF flag will be asserted but the CRG will not wake-up from pseudo-stop mode.
If any other interrupt source (e.g. RTI) triggers exit from pseudo-stop mode the MCU immediately
continues with normal operation. Because the PLL has been powered-down during stop mode the PLLSEL
bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL
bit again, in order to switch system and core clocks to the PLLCLK.
Table 9-12
summarizes the outcome of a clock loss while in pseudo-stop mode.
280
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24