MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 206

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 7 Debug Module (DBGV1) Block Description
7.3.2.8
1. In DBG mode, BKAMBH:BKAMBL has no meaning and are forced to 0’s.
2. In DBG mode, BKBMBH:BKBMBL are used in full mode to qualify data.
206
Module Base + 0x0029
Starting address location affected by INITRG register setting.
RWCEN
BKCEN
TAGAB
Reset
TAGC
Field
RWC
4
3
2
1
0
W
R
BKAMBH
Comparator A/B Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction
boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause
a tagged breakpoint.
0 On match, break at the next instruction boundary (force)
1 On match, break if/when the instruction is about to be executed (tagged)
Breakpoint Comparator C Enable Bit — This bit enables the breakpoint capability using comparator C.
0 Comparator C disabled for breakpoint
1 Comparator C enabled for breakpoint
Note: This bit will be cleared automatically when the DBG module is armed in loop1 mode.
Comparator C Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction
boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause
a tagged breakpoint.
0 On match, break at the next instruction boundary (force)
1 On match, break if/when the instruction is about to be executed (tagged)
Read/Write Comparator C Enable Bit — The RWCEN bit controls whether read or write comparison is enabled
for comparator C. RWCEN is not useful for tagged breakpoints.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for
comparator C. The RWC bit is not used if RWCEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Debug Control Register 3 (DBGC3)
0
7
(1)
BKAMBL
0
6
Table 7-14. DBGC2 Field Descriptions (continued)
Figure 7-14. Debug Control Register 3 (DBGC3)
1
BKBMBH
MC9S12C-Family / MC9S12GC-Family
0
5
(2)
BKBMBL
Rev 01.24
0
4
Description
2
RWAEN
0
3
RWA
0
2
RWBEN
Freescale Semiconductor
0
1
RWB
0
0