MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 254

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.2.3
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
9.3
This section provides a detailed description of all registers accessible in the CRGV4.
9.3.1
Table 9-1
254
1. CTFLG is intended for factory test purposes only.
2. FORBYP is intended for factory test purposes only.
3. CTCTL is intended for factory test purposes only.
Memory Map and Register Definition
Address
gives an overview on all CRGV4 registers.
0x000A
0x000B
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
Offset
RESET — Reset Pin
Module Memory Map
CRG Synthesizer Register (SYNR)
CRG Reference Divider Register (REFDV)
CRG Test Flags Register (CTFLG)
CRG Flags Register (CRGFLG)
CRG Interrupt Enable Register (CRGINT)
CRG Clock Select Register (CLKSEL)
CRG PLL Control Register (PLLCTL)
CRG RTI Control Register (RTICTL)
CRG COP Control Register (COPCTL)
CRG Force and Bypass Test Register (FORBYP)
CRG Test Control Register (CTCTL)
CRG COP Arm/Timer Reset (ARMCOP)
Figure 9-2. PLL Loop Filter Connections
MCU
MC9S12C-Family / MC9S12GC-Family
Table 9-1. CRGV4 Memory Map
XFC
Rev 01.24
(1)
(3)
Use
RS
CS
(2)
CP
V
DDPLL
Freescale Semiconductor
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W