MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 209

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.3.2.9
1. See
2. See
Freescale Semiconductor
Module Base + 0x002A
Starting address location affected by INITRG register setting.
DBG
BKP
EXTCMP
comparators A and B in DBG mode only).
PAGSEL
Reset
Field
7:6
5:0
(1)
(2)
Figure
Figure 7-10
W
R
Not FLASH/ROM access
7-16.
Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in
20.
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively).
In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address
is in the FLASH/ROM memory space.
Comparator A Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in
FLASH/ROM access
Debug Comparator A Extended Register (DBGCAX)
0
7
Table 7-20
Mode
PAGSEL = 00
PAGSEL = 01
(note that while this figure provides extended comparisons for comparator C, the figure also pertains to
PAGSEL
Figure 7-15. Debug Comparator A Extended Register (DBGCAX)
along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core.
0
6
Table 7-20. Comparator A or B Compares
Table 7-19. DBGCAX Field Descriptions
MC9S12C-Family / MC9S12GC-Family
0
5
EXTCMP[5:0] = XAB[19:14]
EXTCMP[5:0] = XAB[21:16]
EXTCMP Compare
No compare
No compare
Rev 01.24
0
4
Description
0
3
Chapter 7 Debug Module (DBGV1) Block Description
EXTCMP
DBGCxH[7:0] = XAB[15:14], AB[13:8]
0
2
DBGCxH[7:0] = AB[15:8]
DBGCxH[5:0] = AB[13:8]
DBGCxH[7:0] = AB[15:8]
High-Byte Compare
0
1
Table 7-
0
0
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