MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 109

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 3
Module Mapping Control (MMCV4) Block Description
3.1
This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core
platform.
The block diagram of the MMC is shown in
The MMC is the sub-module which controls memory map assignment and selection of internal resources
and external space. Internal buses between the core and memories and between the core and peripherals is
controlled in this module. The memory expansion is generated in this module.
Freescale Semiconductor
EBI ALTERNATE WRITE DATA BUS
EBI ALTERNATE READ DATA BUS
EBI ALTERNATE ADDRESS BUS
READ & WRITE ENABLES
CPU WRITE DATA BUS
CPU READ DATA BUS
MODE INFORMATION
CPU ADDRESS BUS
BDM_UNSECURE
CLOCKS, RESET
CPU CONTROL
Introduction
STOP, WAIT
SECURE
REGISTERS
MC9S12C-Family / MC9S12GC-Family
Figure 3-1. MMC Block Diagram
Figure
BUS CONTROL
SECURITY
Rev 01.24
MMC
3-1.
INTERNAL MEMORY
ADDRESS DECODE
EXPANSION
ALTERNATE WRITE DATA BUS (BDM)
ALTERNATE READ DATA BUS (BDM)
ALTERNATE ADDRESS BUS (BDM)
MEMORY SPACE SELECT(S)
PERIPHERAL SELECT
PORT K INTERFACE
CORE SELECT (S)
MMC_SECURE
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