MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 300

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
1. Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds
2. To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs,
300
RSTAT[1:0]
TSTAT[1:0]
a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state
skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.
reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition.
WUPIF
CSCIF
OVRIF
RXF
Field
5:4
3:2
7
6
1
0
(2)
Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see
“MSCAN Sleep
(CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set.
0
1
CAN Status Change Interrupt Flag — This flag is set when the MSCAN changes its current CAN bus status
due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-
bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system
on the actual CAN bus status (see
If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking interrupt. That
guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change
interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause
an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt
is cleared again.
0
1
Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As
soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN
bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:
00
01
10
11
Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN.
As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related
CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:
00
01
10
11
Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt
is pending while this flag is set.
0
1
Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This
flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier,
matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message
from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag
prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt
is pending while this flag is set.
0
1
No wake-up activity observed while in sleep mode
MSCAN detected activity on the CAN bus and requested wake-up
No change in CAN bus status occurred since last interrupt
MSCAN changed current CAN bus status
RxOK: 0 ≤ receive error counter ≤ 96
RxWRN: 96 < receive error counter ≤ 127
RxERR: 127 < receive error counter
Bus-off
TxOK: 0 ≤ transmit error counter ≤ 96
TxWRN: 96 < transmit error counter ≤ 127
TxERR: 127 < transmit error counter ≤ 255
Bus-Off: transmit error counter > 255
No data overrun condition
A data overrun detected
No new message available within the RxFG
The receiver FIFO is not empty. A new message is available in the RxFG
(1)
: transmit error counter > 255
Mode,”) and WUPE = 1 in CANTCTL0 (see
Table 10-9. CANRFLG Register Field Descriptions
MC9S12C-Family / MC9S12GC-Family
Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register
Rev 01.24
Description
Section 10.3.2.1, “MSCAN Control Register 0
Freescale Semiconductor
Section 10.4.5.4,
(CANRIER)”).