ATTINY24A-PU Atmel, ATTINY24A-PU Datasheet - Page 36

• Manufacturer Part Number: ATTINY24A-PU
• Description: MCU AVR 2K FLASH 20MHZ 14PDIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 20 Channel
• Data Rom Size: 128 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 20
• Height: 5.33 mm
• Length: 19.68 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 7.11 mm
• For Use With: ATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.5
7.4.6
7.5
7.5.1
36
Register Description
ATtiny24A/44A/84A
Watchdog Timer
Port Pins
MCUCR – MCU Control Register
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. See
Reference” on page 41
If the Watchdog Timer is not needed in the application, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. See
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
both the I/O clock (clk
will be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. See the section
which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an
analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). See
“DIDR0 – Digital Input Disable Register 0” on page 149
The MCU Control Register contains control bits for power management.
• Bit 7 – BODS: BOD Sleep
In order to disable BOD during sleep (see
logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First,
both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be
set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is
set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for
the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.
In devices where Sleeping BOD has not been implemented this bit is unused and will always
read zero.
• Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
Bit
0x35 (0x55)
Read/Write
Initial Value
“Watchdog Timer” on page 41
CC
BODS
R/W
7
0
/2 on an input pin can cause significant current even in active mode. Digital
I/O
for details on the start-up time.
) and the ADC clock (clk
PUD
R/W
6
0
“Digital Input Enable and Sleep Modes” on page 56
CC
/2, the input buffer will use excessive power.
R/W
SE
5
0
for details on how to configure the Watchdog Timer.
Table 7-1 on page
SM1
R/W
4
0
ADC
) are stopped, the input buffers of the device
SM0
R/W
3
0
for details.
BODSE
33) the BODS bit must be written to
R/W
2
0
ISC01
R/W
1
0
ISC00
“Internal Voltage
R/W
0
0
for details on
8183C–AVR–03/11
MCUCR