ATTINY24A-PU Atmel, ATTINY24A-PU Datasheet - Page 113

• Manufacturer Part Number: ATTINY24A-PU
• Description: MCU AVR 2K FLASH 20MHZ 14PDIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 20 Channel
• Data Rom Size: 128 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 20
• Height: 5.33 mm
• Length: 19.68 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 7.11 mm
• For Use With: ATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. Timer/Counter Prescaler
13.1
13.2
8183C–AVR–03/11
Prescaler Reset
External Clock Source
Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counters. Tn
is used as a general name, n = 0, 1.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/CounterCounter, and it is shared by the Timer/Counter Tn. Since the prescaler is not
affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for
situations where a prescaled clock is used. One example of prescaling artifacts occurs when the
timer is enabled and clocked by the prescaler (CSn[2:0] = 2, 3, 4, or 5). The number of system
clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 sys-
tem clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
shows a functional equivalent block diagram of the Tn synchronization and edge detector logic.
The registers are clocked at the positive edge of the internal system clock (
transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn[2:0] = 6) edge it detects.
Figure 13-1.
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
CLK_I/O
Tn
clk
I/O
/256, or f
CLK_I/O
D
LE
T0 Pin Sampling
Q
/1024.
Synchronization
CLK_I/O
D
Q
). Alternatively, one of four taps from the prescaler can be used
T
0
pulse for each positive (CSn[2:0] = 7) or negative
ATtiny24A/44A/84A
D
Q
Figure 13-1 on page 113
CLK_I/O
Edge Detector
clk
I/O
/8, f
). The latch is
CLK_I/O
Tn_sync
(To Clock
Select Logic)
Tn
). The
/64,
113