ATTINY24A-PU Atmel, ATTINY24A-PU Datasheet - Page 163

• Manufacturer Part Number: ATTINY24A-PU
• Description: MCU AVR 2K FLASH 20MHZ 14PDIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 20 Channel
• Data Rom Size: 128 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 20
• Height: 5.33 mm
• Length: 19.68 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 7.11 mm
• For Use With: ATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.5.1
8183C–AVR–03/11
Serial Programming Algorithm
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
When writing serial data to the ATtiny24A/44A/84A, data is clocked on the rising edge of SCK.
When reading, data is clocked on the falling edge of SCK. See
timing details.
To program and verify the ATtiny24A/44A/84A in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in
• Low:> 2 CPU clock cycles for f
• High:> 2 CPU clock cycles for f
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse after SCK has been set to '0'. The duration
of the pulse must be at least t
20-4 on page
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program memory
Page is stored by loading the Write Program memory Page instruction with the 3 MSB
of the address. If polling (RDY/BSY) is not used, the user must wait at least t
before issuing the next page. (See
gramming interface before the Flash write operation completes can result in incorrect
programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY) is not used,
the user must wait at least t
page
grammed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the
Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by
loading the Write EEPROM Memory Page Instruction with the 4 MSB of the address.
When using EEPROM page access only byte locations loaded with the Load EEPROM
Memory Page instruction is altered. The remaining locations remain unchanged. If poll-
ing (RDY/BSY) is not used, the used must wait at least t
next page (See
file(s) need to be programmed.
content at the selected address at serial output MISO.
164.) In a chip erased device, no 0xFFs in the data file(s) need to be pro-
176) plus two CPU clock cycles.
Table 19-11 on page
CC
and GND while RESET and SCK are set to “0”. In some sys-
WD_EEPROM
ck
ck
RST
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
(the minimum pulse width on RESET pin, see
Table 19-11 on page
164). In a chip erased device, no 0xFF in the data
before issuing the next byte. (See
ATtiny24A/44A/84A
WD_EEPROM
164.) Accessing the serial pro-
Table
Figure 20-3
19-12):
ck
ck
before issuing the
>= 12 MHz
>= 12 MHz
and
Table 19-11 on
Figure 20-4
WD_FLASH
Table
163
for