UJA1065 NXP Semiconductors, UJA1065 Datasheet
UJA1065
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UJA1065 Summary of contents
Page 1
... In failure situations, the fail-safe SBC will maintain microcontroller functionality for as long as possible to provide full monitoring and a software-driven fall-back operation. The UJA1065 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures. Product data sheet ...
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... LIN transceiver LIN 2.0 compliant LIN transceiver Enhanced error signalling and reporting Downward compatible with LIN 1.3 and the TJA1020 UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip Rev. 07 — 25 February 2010 UJA1065 © NXP B.V. 2010. All rights reserved ...
Page 3
... Fail-safe mode (e.g. for switching on warning lights) Fail-safe coded activation of Software development mode and Flash mode Unique SPI readable device type identification Software-initiated system reset UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip Rev. 07 — 25 February 2010 UJA1065 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information [1] Type number Package Name UJA1065TW HTSSOP32 [1] UJA1065TW/5V0 is for the 5 V version; UJA1065TW/3V3 is for the 3.3 V version. 4. Block diagram 31 SENSE 32 BAT42 27 BAT14 29 SYSINH INH/LIMP 7 INTN 18 WAKE WAKE 16 TEST CHIP TEMPERATURE 11 SCK 9 SDI SPI 10 SDO 12 SCS ...
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... SPI chip select input (active LOW) 13 CAN transmit data input (LOW for dominant; HIGH for recessive) 14 CAN receive data output (LOW when dominant; HIGH when recessive) 15 not connected 16 test pin (should be connected to ground in application) Rev. 07 — 25 February 2010 UJA1065 32 BAT42 31 SENSE SYSINH 28 n ...
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... V output (BAT42 related; continuous output, or Cyclic mode synchronized with local wake-up input) 31 fast battery interrupt / chatter detector input battery supply input (connect this pin to BAT14 applications) Rev. 07 — 25 February 2010 UJA1065 © NXP B.V. 2010. All rights reserved ...
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... Fail-safe behavior 6.2 Fail-safe system controller The fail-safe system controller is the core of the UJA1065 and is supervised by a watchdog timer that is clocked directly by the dedicated on-chip oscillator. The system controller manages the register configuration and controls all internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. ...
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... OR V1 undervoltage detected OR illegal Mode register code CAN: all modes available INH/LIMP: HIGH/LOW/float oscillator fail OR RSTN externally clamped HIGH detected > RSTN externally clamped LOW detected > undervoltage detected > t V1(CLT) UJA1065 Sleep mode V1: OFF SYSINH: HIGH/float LIN: off-line INH/LIMP: LOW/float RSTN: LOW EN: LOW watchdog ...
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... During the reset lengthening time pin RSTN is held to the higher value to guarantee the maximum reset length, RSTNL , to guarantee a discharged V1 before ret Section 6.5.1. Rev. 07 — 25 February 2010 UJA1065 is observed. This reset time is RSTNL RSTNL . RSTN(INT) © NXP B.V. 2010. All rights reserved. is ...
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... possible to exit Standby mode without any system reset if required. UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip , e.g. as result of a microcontroller wake-up from thH(V1) Rev. 07 — 25 February 2010 UJA1065 © NXP B.V. 2010. All rights reserved ...
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... Wake-up by activity on the CAN-bus, LIN-bus or falling edge at pin WAKE • An overload on V3, only cyclic or in continuously on mode UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip . Otherwise a fail-safe system reset is forced and Start-up mode will be Rev. 07 — 25 February 2010 UJA1065 © NXP B.V. 2010. All rights reserved ...
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... To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are coded with redundant bits. Therefore, only certain codes are allowed for a proper watchdog service. UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip Rev. 07 — 25 February 2010 UJA1065 WD(init) © NXP B.V. 2010. All rights reserved ...
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... Watchdog triggering using Window mode Rev. 07 — 25 February 2010 UJA1065 , another reset is forced WD(init) Figure 3, Start-up and Restart trigger window 100 % latest possible trigger point desired) ...
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... Watchdog triggering using Time-out mode Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip 5. The Time-out mode can be used to provide time-out latest possible trigger point trigger range new period UJA1065 time-out mce627 . thL(V1) © NXP B.V. 2010. All rights reserved ...
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... In case of a direct mode change towards Standby mode with watchdog OFF selected, the longest possible watchdog period is used. It should be noted that in Sleep mode V1 current monitoring is not active. 6.5 System reset The reset function of the UJA1065 offers two signals to deal with reset events: • RSTN; the global ECU system reset • ...
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... Reset timing diagram Rev. 07 — 25 February 2010 Figure 6. The duration of t RSTNL missing under- watchdog voltage access spike t RSTNL time t WD(init) time t WD(init) 001aad181 UJA1065 depends on the V rel(UV)(V1) V det(UV)(V1) time power- down time coa054 © NXP B.V. 2010. All rights reserved ...
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... Connecting this pin in front of the polarity protection diode of the ECU provides an early warning if the battery becomes disconnected. 6.6.3 Voltage regulators V1 and V2 The UJA1065 has two independent voltage regulators supplied out of the BAT14 pin. Regulator V1 is intended to supply the microcontroller. Regulator V2 is reserved for the high-speed CAN transceiver. ...
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... Status register. This signals that the wake-up source via V3 supplied wake-up switches has been lost. UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip . This allows the application to receive a supply warning interrupt in UV(VFI) Rev. 07 — 25 February 2010 UJA1065 ), V2(CLT) © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 6.7 CAN transceiver The integrated high-speed CAN transceiver of the UJA1065 is an advanced ISO 11898-2 and ISO 11898-5 compliant transceiver. In addition to standard high-speed CAN transceivers the UJA1065 transceiver provides the following features: • Enhanced error handling and reporting of bus and RXD/TXD failures; these failures are separately identified in the System Diagnosis register • ...
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... AND CPNC = 1 no activity for t > t Off-line mode V2: ON/OFF (V2C/V2D) transmitter: OFF RXDC: V1 SPLIT: OFF CPNC = Rev. 07 — 25 February 2010 UJA1065 On-line Listen mode Normal mode V2: ON/OFF (V2C/V2D) OR Flash mode transmitter: OFF AND CMC = 1 RXDC: V1 SPLIT: ON/OFF (CSC/V2D) CPNC = 1 off-line 001aad182 © ...
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... When entering On-line (Listen) mode from Off-line mode the CAN off-line time is temporarily extended to t 6.7.2 CAN wake-up To wake-up the UJA1065 via CAN it has to be distinguished between a conventional wake-up and a global wake-up in case partial networking is enabled (bit CPNC = 1). To pass the wake-up filter for a conventional wake-up a dominant, recessive, dominant, recessive signal on the CAN-bus is needed ...
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... Bus, RXD and TXD failure detection The UJA1065 can distinguish between bus, RXD and TXD failures as indicated in All failures are signalled separately in the CANFD bits in the System Diagnosis register. Any change (detection and recovery) forces an interrupt to the microcontroller, if this interrupt is enabled ...
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... System Diagnosis register. Any detected or recovered GND shift event is signalled with an interrupt, if enabled. 6.8 LIN transceiver The integrated LIN transceiver of the UJA1065 is a LIN 2.0 compliant transceiver. The transceiver has the following features: • SAE J2602 compliant and compatible with LIN revision 1.3 • ...
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... Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip t BUS(LIN) 001aad447 LIN(dom)(det) RTLIN = 75 μA supplied directly out of BAT42 LIN(dom)(rec) Off-line mode LIN(dom)(rec) Off-line mode AND receiver dominant > t LIN(dom)(det) 001aad183 UJA1065 Figure 11. © NXP B.V. 2010. All rights reserved ...
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... UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip the transmitter is disabled BAT14 BAT42 ), the state of the LIN termination is changed according to Rev. 07 — 25 February 2010 UJA1065 the LIN transmitter is TXDL(dom)(dis) (which is longer than LIN(dom)(det) Figure 12. Figure 13. © NXP B.V. 2010. All rights reserved. ...
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... OR enter Fail-safe mode OR enter Restart mode OR enter Sleep mode INH/LIMP: floating ILEN = 0 power-on ILC = 1/0 Rev. 07 — 25 February 2010 INH/LIMP: LOW ILEN = 1 ILC = 0 state change via SPI state change via SPI 001aad178 UJA1065 ensures a BAT42 Figure 14. © NXP B.V. 2010. All rights reserved ...
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... INTN stays HIGH, otherwise it will revert to LOW again. INTN 6.13.7. RSTN(INT) Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip button released signal remains LOW due to biasing (history) a system reset is performed. UJA1065 001aac307 © NXP B.V. 2010. All rights reserved ...
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... SCK 01 sampled SDI X SDO X floating Fig 15. SPI timing protocol UJA1065_7 Product data sheet Figure 15 MSB 14 13 MSB 14 13 Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip LSB 12 01 LSB UJA1065 X floating mce634 © NXP B.V. 2010. All rights reserved ...
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... Physical Layer Control Physical Layer Control register Feedback register General Purpose register 1 Physical Layer Control Feedback register Rev. 07 — 25 February 2010 UJA1065 Figure 3 result in an immediate system reset Section 6.13.3 Table 4. The first two bits (A1 and Read Register Select (RRS) bit = 1 ...
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... EN output pin HIGH 0 EN output pin LOW 0 reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit Rev. 07 — 25 February 2010 UJA1065 from releasing WD(init) [1] [2] after system reset) the SBC will WD(init) © NXP B.V. 2010. All rights reserved. ...
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... OFF Rev. 07 — 25 February 2010 UJA1065 Flash mode Sleep mode (ms) (ms) 20 160 40 320 80 640 160 1024 320 2048 640 3072 1024 4096 2048 ...
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... OFF 28672 UJA1065 Sleep mode (ms) 560 1120 2240 3584 7168 10752 14336 21504 28672 [3] OFF = 512 kHz. osc © NXP B.V. 2010. All rights reserved ...
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... Software Development mode off 1 pin EN output activated (V1-related HIGH level) 0 pin EN output released (LOW level) 1 power-on reset; cleared after a successfully entered Normal mode 0 no power-on reset Rev. 07 — 25 February 2010 UJA1065 exceeded WD(init) RSTN(INT) © NXP B.V. 2010. All rights reserved ...
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... V3 is disabled due to an overload situation [ fail disabled due to an overload situation 1 OK; V1 always above V 0 fail; V1 was below V again with read access Rev. 07 — 25 February 2010 UJA1065 , BAT14 BAT42 , BAT14 BAT42 since last read access UV(VFI) since last read access; bit is set UV(VFI) © ...
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... V1D, V2D or V3D forces an interrupt 0 no interrupt forced 1 any change of the CAN Failure status bits forces an interrupt 0 no interrupt forced 1 any change of the LIN Failure status bits forces an interrupt 0 no interrupt forced Rev. 07 — 25 February 2010 UJA1065 © NXP B.V. 2010. All rights reserved ...
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... Normal or Flash mode (unless LIN is in Active mode already) 0 LIN-bus event results in a reset in Standby mode; no interrupt in any other mode Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip …continued to guarantee an edge event at pin INTN UJA1065 © NXP B.V. 2010. All rights reserved ...
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... A watchdog restart during watchdog OFF has caused an interrupt 0 no interrupt 1 CAN wake-up event has caused an interrupt 0 no interrupt 1 LIN wake-up event has caused an interrupt 0 no interrupt Rev. 07 — 25 February 2010 UJA1065 © NXP B.V. 2010. All rights reserved ...
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... INH/LIMP pin active (See ILC bit) 0 INH/LIMP pin floating 1 INH/LIMP pin HIGH if ILEN bit is set 0 INH/LIMP pin LOW if ILEN bit is set Rev. 07 — 25 February 2010 UJA1065 widened threshold normal threshold long period; see Figure 14 w(CS) short period; see Figure 14 w(CS) © NXP B.V. 2010. All rights reserved. ...
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... LIN-bus enabled 0 wake-up via the LIN-bus disabled 1 LIN transmitter is disabled [3] 0 LIN transmitter is enabled Section 6.7.1.4. Rev. 07 — 25 February 2010 UJA1065 long period (extended to t off-line(ext) short period (extended to t off-line(ext) after wake-up) after wake-up) © NXP B.V. 2010. All rights reserved ...
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... V1RTHC [1:0] V1 Reset Threshold Control reserved [1] See Section 6.14.1. [2] Not supported in the UJA1065TW/3V3 version. UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip Value Function 01 select Special Mode register 0 read the Interrupt Enable Feedback register 1 read the Special Mode Feedback register ...
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... NXP Semiconductors 6.13.11 General Purpose registers and General Purpose Feedback registers The UJA1065 offers two 12-bit General Purpose registers (and accompanying General Purpose Feedback registers) with no predefined bit definition. These registers can be used by the microcontroller for advanced system diagnosis or for storing critical system status information outside the microcontroller. After Power-up General Purpose register 0 will contain a ‘ ...
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... Power-on Start-up 0 (interrupt disabled) no change Power-on Start-up 0 (no interrupt) 0 (no interrupt) Rev. 07 — 25 February 2010 UJA1065 [1] [1] Restart 0000 or 0010 or 1100 or 1110 no change no change no change actual status actual status actual status 0 if ERREM = 0, otherwise actual CAN failure status ...
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... Rev. 07 — 25 February 2010 UJA1065 Restart Fail-Safe no change no change 1 (long) 1 (long) no change no change no change no change no change no change no change no change 0 (floating) if ILC = 1, 1 (active) ...
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... High-speed CAN/LIN fail-safe system basis chip Power-on 0 (no) 0 (EN function) 00 (factor 1) 00 (90 %) Power-on 0 (Device ID) Mask version 000 0101 (UJA1065) no change Power-on 0000 0000 0000 is the only exception that results in entering Fail-safe mode (to protect the Rev. 07 — 25 February 2010 UJA1065 Start-up Restart no change ...
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... Mode register. Reentering the Software development mode is only possible by reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset. 6.14.2 Forced normal mode For system evaluation purposes the UJA1065 offers the Forced normal mode. This mode is strictly for evaluation purposes only. In this mode the characteristics as defined in Section 9 In Forced normal mode the SBC behaves as follows: • ...
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... ISO 7637-3 HBM at pins CANH, CANL, SPLIT, LIN, RTLIN, WAKE, BAT42, V3, SENSE; with respect to GND at any other pin MM; at any pin . The rating for T limits the allowable combinations of power dissipation ( Rev. 07 — 25 February 2010 UJA1065 Min Max Unit −0.3 + +60 V −0.3 + ...
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... RTLIN LIN LIN in Active mode; LMC = < t TXDL LIN(dom)(det RTLIN LIN BAT42 BAT42 Rev. 07 — 25 February 2010 UJA1065 V3 dissipation other dissipation 23 K/W 6 K/W T (heat sink) case R th(c-a) T amb 001aac327 ≥ − unless otherwise specified. All BAT42 BAT14 [1] Min Typ ...
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... Normal mode; BATFIE = 1 Standby mode; BATFIE = 1 Normal mode or Standby mode; BATFIE = 0 Figure 17 to Figure 5 BAT14 = −120 mA to −5 mA ° −5 mA BAT14 ° Rev. 07 — 25 February 2010 UJA1065 ≥ − unless otherwise specified. All BAT42 BAT14 [1] Min Typ Max 4. 4. 200 300 - 150 ...
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... V V1 V1(nom BAT14 V1 shorted to GND BAT14 δV = 0.05 × V1(nom 5 BAT14 δV = 0.05 × V1(nom BAT14 Rev. 07 — 25 February 2010 UJA1065 ≥ − unless otherwise specified. All BAT42 BAT14 [1] Min Typ Max - [ 200 0.90 × 0.92 × 0.95 × ...
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... Typ 4.8 5.0 4. −200 - −300 - - - - - 4.5 4 −165 - - 0.7 - 1.2 0 2.0 3.3 −25 - UJA1065 Max Unit 5 200 ppm/K −120 −80 mA −50 mA 4.8 V 1.0 V −60 mA μA 5 2.0 V μA 5 1 μA 5 5.2 V −1.3 μA © NXP B.V. 2010. All rights reserved. ...
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... Min Typ 0.7 × −0 130 50 130 −5 - −50 - 1.6 - − −1000 - 0.7 × −0.3 - − 1.6 - 0.7 × −0.3 - UJA1065 Max Unit +0.3 × 400 kΩ 400 kΩ μA +5 −1 μA +5 −50 μ 0.2 × 0 +0.3 × −1 0 0.3 ...
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... UJA1065 Max Unit 25 kΩ − +50 mV 2.75 V +0.1 V 0.9 V 1.15 V 2.45 V 1.5 V −45 mA © NXP B.V. 2010. All rights reserved. ...
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... Min Typ ; 45 75 −5 - − − [ [ 0.3 × V 0.5 × −10 0 −0.3 - 0.7 × −50 - UJA1065 Max Unit 100 μA +10 28 kΩ 40 kΩ kΩ Ω 50 0.7 × μA +10 +0.3 × 0 kΩ −1.6 mA © NXP B.V. 2010. All rights reserved. ...
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... V BAT42 0.475 × 0.500 × BAT42 BAT42 [ −5 0 −10 0 − − BAT42 BAT42 1.0 0.7 − − BAT42 BAT42 1.2 1.0 UJA1065 Max Unit 20 mA 0.20 × BAT42 2.1 V μA +10 μA +10 μ 0.4 × BAT42 - V 0.175 × BAT42 0.525 × ...
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... RTLIN LIN t > t LIN(dom)(det) for entering Software development mode ° for entering Forced normal = 25 °C mode between pin TEST and GND Rev. 07 — 25 February 2010 UJA1065 ≥ − unless otherwise specified. All BAT42 BAT14 [1] Min Typ Max - 0.65 2 −150 −60 − ...
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... −100 μA −50 mA −120 mA −250 150 °C. j Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip type 5V0 type 3V3 type 5V0 type 3V3 UJA1065 015aaa055 7 (V) BAT14 015aaa056 7 (V) BAT14 © NXP B.V. 2010. All rights reserved ...
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... ( BAT14 2 (2) 5 −50 −100 0 = −40 °C to +150 °C. j Rev. 07 — 25 February 2010 UJA1065 001aaf246 = +150 ° −40 ° +25 °C +150 °C +25 °C −40 °C −150 −200 −250 I (mA) V1 001aaf247 −150 −200 −250 I (mA) V1 © ...
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... T j 160 BAT14 120 = 25 ° °C to 150 °C 5.5 V (1) 5 −120 mA Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip −80 −120 I V1 150 °C 150 ° (Hz) UJA1065 015aaa057 −160 (mA) 001aaf248 3 10 © NXP B.V. 2010. All rights reserved ...
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... V1 − 100 200 = μF; ESR = 0.01 Ω BAT14 Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip 300 400 = 25 °C. j 300 400 = 25 °C. j UJA1065 001aaf250 200 ΔV V1 (mV) 100 Δ −100 500 t (μs) 001aaf251 400 ΔV V1 (mV) 200 Δ −200 500 t (μ ...
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... Fig 22. V1 output stability related to ESR value of output capacitor UJA1065_7 Product data sheet 1 (Ω) −1 10 −2 10 unstable operation area −3 10 −40 0 Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip stable operation area −80 I (mA) V1 UJA1065 001aaf249 −120 © NXP B.V. 2010. All rights reserved ...
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... High-speed CAN/LIN fail-safe system basis chip load SBC 47 μF/ 100 0.1 Ω nF GND 0.8 1.2 1.6 0.8 1.2 1.6 UJA1065 R load 001aaf572 015aaa058 type 5V0 type 3V3 2.0 t (ms) 015aaa059 type 5V0 type 3V3 2.0 t (ms) © NXP B.V. 2010. All rights reserved ...
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... C = 100 pF Ω; see Figure 25 and Figure 26 Active mode, On-line mode or On-line Listen mode TXDC Off-line mode Off-line mode Off-line mode On-line Listen mode Rev. 07 — 25 February 2010 UJA1065 − unless otherwise specified. All BAT14 Min Typ Max [2] 24) 960 - - 240 - - 240 ...
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... BAT42 RXDL rising edge with respect to falling edge RXDL Off-line mode Active mode; LIN = 0 V Active mode Active mode; TXDL = 0 V Rev. 07 — 25 February 2010 UJA1065 ≥ − unless otherwise specified. All BAT42 BAT14 [1] Min Typ Max 200 - 265 ...
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... RSTN pin remains HIGH RSTN driven HIGH internally but RSTN pin remains LOW INTN = 0 after internal or external reset has been released; RLC = 0 after internal or external reset has been released; RLC =1 Rev. 07 — 25 February 2010 UJA1065 ≥ − unless otherwise specified. All BAT42 BAT14 [1] Min ...
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... V the guaranteed SPI timing values double, BAT42 Figure 27 and Figure t T lead cyc t t SCKH SCKL MSB X floating X MSB Rev. 07 — 25 February 2010 UJA1065 ≥ − unless otherwise specified. All BAT42 BAT14 [1] Min Typ Max 460.8 512 563.2 28. t lag LSB t DOV LSB © ...
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... UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip BAT42 RXDC 10 pF TXDC GND TXDC CANH CANL V o(dif) RXDC t t(reces-dom) t PHL Rev. 07 — 25 February 2010 UJA1065 BAT14 CANH R C SBC CANL 001aac308 HIGH LOW dominant recessive HIGH LOW t t(dom-reces) t PLH 001aac309 © ...
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... SBC 20 pF TXDL LIN GND t bit t t bus(dom)(max) bus(rec)(min bus(dom)(min) bus(rec)(max) t p(rx)r t p(rx)r Rev. 07 — 25 February 2010 UJA1065 001aad179 t bit V th(reces)(max) thresholds of V receiving node 1 th(dom)(max) V th(reces)(min) thresholds of receiving node 2 V th(dom)(min) t p(rx)f 001aaa346 © ...
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... REFERENCES JEDEC JEITA MO-153 Rev. 07 — 25 February 2010 detail 8.3 0.75 0.65 1 0.2 0.1 7.9 0.50 EUROPEAN PROJECTION UJA1065 SOT549 θ θ 0.78 8 0.1 o 0.48 0 ISSUE DATE 03-04-07 05-11-02 © NXP B.V. 2010. All rights reserved ...
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... Solder bath specifications, including temperature and impurities UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip Rev. 07 — 25 February 2010 UJA1065 © NXP B.V. 2010. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 30. Rev. 07 — 25 February 2010 UJA1065 Figure 30) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2010. All rights reserved. ...
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... Product data sheet High-speed CAN/LIN fail-safe system basis chip maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level Rev. 07 — 25 February 2010 UJA1065 peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 14. Revision history Table 30. Revision history Document ID Release date UJA1065_7 20100225 • Modifications: 3.0 V version (UJA1065TW/3V0) discontinued • Section • Table 11: text of bit 4, V1CMC, revised • Section • Section UJA1065_6 20071122 UJA1065_5 20061116 UJA1065_4 20060818 UJA1065_3 20060221 UJA1065_2 20051216 UJA1065_1 ...
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... In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Rev. 07 — 25 February 2010 UJA1065 © NXP B.V. 2010. All rights reserved ...
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... Product data sheet High-speed CAN/LIN fail-safe system basis chip 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 07 — 25 February 2010 UJA1065 © NXP B.V. 2010. All rights reserved ...
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... Test modes 6.14.1 Software development mode . . . . . . . . . . . . . 44 6.14.2 Forced normal mode . . . . . . . . . . . . . . . . . . . 45 7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 46 8 Thermal characteristics . . . . . . . . . . . . . . . . . 47 9 Static characteristics . . . . . . . . . . . . . . . . . . . 47 10 Dynamic characteristics Test information . . . . . . . . . . . . . . . . . . . . . . . 67 11.1 Quality information . . . . . . . . . . . . . . . . . . . . . 67 Rev. 07 — 25 February 2010 UJA1065 continued >> © NXP B.V. 2010. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UJA1065 All rights reserved. Date of release: 25 February 2010 Document identifier: UJA1065_7 ...