UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 62

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
10. Dynamic characteristics
Table 27.
T
voltages are defined with respect to ground. Positive currents flow into the IC.
UJA1065_7
Product data sheet
Symbol
Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see
T
t
t
t
t
t
t
t
t
CAN transceiver timing; pins CANL, CANH, TXDC and RXDC
t
t
t
t
t
t
t
t
t
t
t
t
lead
lag
SCKH
SCKL
su
h
DOV
SSH
t(reces-dom)
t(dom-reces)
PHL
PLH
TXDC(dom)
CANH(dom1)
CANL(dom1)
CANH(reces)
CANL(reces)
CANH(dom2)
CANL(dom2)
timeout
vj
cyc
=
−
40
°
C to +150
,
,
,
Dynamic characteristics
Parameter
clock cycle time
enable lead time
enable lag time
clock HIGH time
clock LOW time
input data setup time
input data hold time
output data valid time
SPI select HIGH time
output transition time
recessive to dominant
output transition time
dominant to recessive
propagation delay TXDC to
RXDC (HIGH-to-LOW
transition)
propagation delay TXDC to
RXDC (LOW-to-HIGH
transition)
TXDC permanent dominant
disable time
minimum dominant time first
pulse for wake-up on pins
CANH and CANL
minimum recessive time
pulse (after first dominant)
for wake-up on pins CANH
and CANL
minimum dominant time
second pulse for wake-up on
pins CANH, CANL
time-out period between
wake-up message and
confirm message
°
C; V
BAT42
= 5.5 V to 52 V; V
Conditions
falls
clock is LOW when SPI select
rises
pin SDO; C
10 % to 90 %; C = 100 pF;
R = 60 Ω; see
Figure 26
90 % to 10 %; C = 100 pF;
R = 60 Ω; see
Figure 26
50 % V
C = 100 pF; R = 60 Ω; see
Figure 25
50 % V
C = 100 pF; R = 60 Ω; see
Figure 25
Active mode, On-line mode or
On-line Listen mode;
V
Off-line mode
Off-line mode
Off-line mode
On-line Listen mode
clock is LOW when SPI select
V2
Rev. 07 — 25 February 2010
BAT14
= 5 V; V
TXDC
TXDC
= 5.5 V to 27 V; V
and
and
L
TXDC
to 50 % V
to 50 % V
= 10 pF
Figure 25
Figure 25
Figure 26
Figure 26
= 0 V
High-speed CAN/LIN fail-safe system basis chip
RXDC
RXDC
and
and
BAT42
;
;
Figure
[1]
≥
V
24)
BAT14
Min
960
240
240
480
480
80
-
480
-
-
70
70
1.5
3
1
1
115
400
[2]
−
1 V; unless otherwise specified. All
Typ
-
-
-
-
-
-
-
-
-
100
100
120
120
-
-
-
-
-
UJA1065
© NXP B.V. 2010. All rights reserved.
Max
-
-
-
-
-
-
-
400
-
-
-
220
220
6
-
-
-
285
62 of 76
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
μs
μs
μs
ms