UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 18

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
UJA1065_7
Product data sheet
6.6.3.2 Voltage regulator V2
6.6.4 Switched battery output V3
A dedicated V1 supply comparator (V1 Monitor) observes V1 for undervoltage events
lower than V
case one of the lower V1 undervoltage reset thresholds is selected.
The V1 regulator is overload protected. The maximum output current available from pin
V1 depends on the voltage applied to pin BAT14 according to the characteristics section.
For thermal reasons, the total power dissipation should be taken into account.
Voltage regulator V2 provides a 5 V supply for the CAN transmitter. The pin V2 is intended
for the connection of external buffering capacitors.
V2 is controlled autonomously by the CAN transceiver control system and is activated on
any detected CAN-bus activity, or if the CAN transceiver is enabled by the application
microcontroller. V2 is short-circuit protected and will be disabled in case of an overload
situation. Dedicated bits in the System Diagnosis register and the Interrupt register
provide V2 status feedback to the application.
Besides the autonomous control of V2 there is a software accessible bit which allows
activation of V2 manually (V2C). This allows V2 to be used for other application purposes
when CAN is not actively used (e.g. while CAN is off-line). Generally, V2 should not be
used for other application hardware while CAN is in use.
If the regulator V2 is not able to start within the V2 clamped LOW time (> t
short-circuit has been detected during an already activated V2, then V2 is disabled and
the V2D bit in the System Diagnosis register is cleared. Additionally the CTC bit in the
Physical Layer Control register is set and the V2C bit is cleared.
Reactivation of voltage regulator V2 can be done by:
V3 is a high-side switched BAT42-related output which is used to drive external loads
such as wake-up switches or relays. The features of V3 are as follows:
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Clearing the CTC bit while CAN is in Active mode
Wake-up via CAN while CAN is not in Active mode
Setting the V2C bit
When entering CAN Active mode
Three application-controlled operating modes; On, Off and Cyclic.
Two different cyclic modes allow the supply of external wake-up switches; these
switches are powered intermittently, thus reducing the system’s power consumption in
case a switch is continuously active; the wake-up input of the SBC is synchronized
with the V3 cycle time.
The switch is protected against current overloads. If V3 is overloaded, pin V3 is
automatically disabled. The corresponding System Diagnosis register bit is reset and
an interrupt is forced (if enabled). During Sleep mode, a wake-up is forced and the
corresponding reset source code becomes available in the RSS bits of the System
Status register. This signals that the wake-up source via V3 supplied wake-up
switches has been lost.
UV(VFI)
. This allows the application to receive a supply warning interrupt in
Rev. 07 — 25 February 2010
High-speed CAN/LIN fail-safe system basis chip
UJA1065
© NXP B.V. 2010. All rights reserved.
V2(CLT)
), or if a
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