UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 29

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 4.
UJA1065_7
Product data sheet
Register
address bits
(A1, A0)
00
01
10
11
Register overview
6.13.1 SPI register mapping
6.13.2 Register overview
all modes
Normal mode;
Normal mode;
Operating
mode
Standby mode;
Flash mode
Start-up mode;
Restart mode
Standby mode
Start-up mode;
Restart mode;
Flash mode
Normal mode;
Standby mode
Start-up mode;
Restart mode;
Flash mode
To protect against wrong or illegal SPI instructions, the SBC detects the following SPI
failures:
Any control bit which can be set by software is readable by the application. This allows
software debugging as well as control algorithms to be implemented.
Watchdog serving and mode setting is performed within the same access cycle; this only
allows an SBC mode change whilst serving the watchdog.
Each register carries 12 data bits; the other 4 bits are used for register selection and
read/write definition.
The SPI interface gives access to all SBC registers; see
A0) of the message header define the register address, the third bit is the read register
select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO)
allows ‘read only’ access to one of the feedback registers. Which of the SBC registers can
be accessed also depends on the SBC operating mode.
•
•
•
SPI clock count failure (wrong number of clock cycles during one SPI access): only
16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock
cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC.
In Start-up and Restart mode a reset is forced instead of an interrupt
Forbidden mode changes according to
Illegal Mode register code. Undefined operating mode or watchdog period coding
results in an immediate system reset; see
Write access (RO = 0)
Mode register
Interrupt Enable register
Special Mode register
System Configuration
register
General Purpose register 0
Physical Layer Control
register
General Purpose register 1
Rev. 07 — 25 February 2010
Read access (RO = 0 or RO = 1)
Read Register Select
(RRS) bit = 0
System Status register
Interrupt Enable Feedback
register
Interrupt Enable Feedback
register
System Configuration
Feedback register
System Configuration
Feedback register
Physical Layer Control
Feedback register
Physical Layer Control
Feedback register
High-speed CAN/LIN fail-safe system basis chip
Figure 3
Section 6.13.3
result in an immediate system reset
Table
4. The first two bits (A1 and
Read Register Select
(RRS) bit = 1
System Diagnosis register
Interrupt register
Special Mode Feedback
register
General Purpose Feedback
register 0
General Purpose Feedback
register 0
General Purpose Feedback
register 1
General Purpose Feedback
register 1
UJA1065
© NXP B.V. 2010. All rights reserved.
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