UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 8

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
UJA1065_7
Product data sheet
Fig 3.
watchdog
trigger
CAN: on-line/on-line listen/off-line
INH/LIMP: HIGH/LOW/float
CAN: all modes available
LIN: all modes available
Main state diagram
INH/LIMP: LOW/float
watchdog: window
watchdog: start-up
via SPI successful
init Normal mode
Normal mode
Restart mode
EN: HIGH/LOW
SYSINH: HIGH
SYSINH: HIGH
LIN: off-line
EN: LOW
V1: ON
V1: ON
OR RSTN released and V1 undervoltage detected
OR RSTN released and V1 undervoltage detected
mode change via SPI
flash entry enabled (111/001/111 mode sequence)
OR mode change to Sleep with pending wake-up
via SPI successful
OR RSTN falling edge detected
OR RSTN falling edge detected
init Normal mode
OR illegal Mode register code
OR illegal Mode register code
OR SPI clock count < > 16
OR SPI clock count < > 16
OR watchdog not properly served
OR interrupt ignored > t
mode change via SPI
OR RSTN falling edge detected
OR V1 undervoltage detected
OR illegal Mode register code
supply connected
t > t
t > t
for the first time
WD(init)
WD(init)
watchdog
trigger
Rev. 07 — 25 February 2010
RSTN(INT)
CAN: on-line/on-line listen/off-line
CAN: on-line/on-line listen/off-line
CAN: on-line/on-line listen/off-line
OR watchdog time-out with watchdog timeout interrupt disabled
INH/LIMP: HIGH/LOW/float
INH/LIMP: HIGH/LOW/float
watchdog: time-out/OFF
mode change via SPI
OR watchdog OFF and I
SYSINH: HIGH/float
wake-up detected with its wake-up interrupt disabled
watchdog: start-up
Fail-safe mode
Standby mode
wake-up detected
Start-up mode
AND oscillator ok
INH/LIMP: LOW
EN: HIGH/LOW
OR mode change to Sleep with pending wake-up
SYSINH: HIGH
SYSINH: HIGH
watchdog: OFF
RSTN: LOW
LIN: off-line
LIN: off-line
AND t > t
LIN: off-line
EN: LOW
EN: LOW
V1: OFF
V1: ON
V1: ON
OR interrupt ignored > t
OR RSTN falling edge detected
OR V1 undervoltage detected
OR illegal Mode register code
ret
High-speed CAN/LIN fail-safe system basis chip
V1
> I
OR interrupt ignored > t
thH(V1)
OR RSTN falling edge detected
OR V1 undervoltage detected
OR illegal Mode register code
RSTN(INT)
leave Flash mode code
OR watchdog time-out
with reset option
OR RSTN externally clamped HIGH detected > t
OR RSTN externally clamped LOW detected > t
OR V1 undervoltage detected > t
OR V3 overload detected
OR watchdog time-out
AND flash entry enabled
wake-up detected
init Flash mode via SPI
mode change via SPI
RSTN(INT)
oscillator fail
V1(CLT)
CAN: on-line/on-line listen/off-line
INH/LIMP: HIGH/LOW/float
CAN: all modes available
watchdog: time-out/OFF
LIN: all modes available
INH/LIMP: LOW/float
SYSINH: HIGH/float
watchdog: time-out
EN: HIGH/LOW
SYSINH: HIGH
Sleep mode
Flash mode
UJA1065
RSTN: LOW
LIN: off-line
© NXP B.V. 2010. All rights reserved.
EN: LOW
RSTN(CLT)
V1: OFF
RSTN(CHT)
V1: ON
001aad180
from any
watchdog
mode
trigger
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