UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 15

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
UJA1065_7
Product data sheet
6.5.1 RSTN pin
6.5 System reset
If the microcontroller supply current increases above I
the watchdog is restarted with the last used watchdog period time and a watchdog restart
interrupt is forced, if enabled.
In case of a direct mode change towards Standby mode with watchdog OFF selected, the
longest possible watchdog period is used. It should be noted that in Sleep mode V1
current monitoring is not active.
The reset function of the UJA1065 offers two signals to deal with reset events:
The system reset pin (RSTN) is a bidirectional input/output. Pin RSTN is active LOW with
selectable pulse length upon the following events; see
All of these reset events have a dedicated reset source in the System Status register to
allow distinction between the different events.
The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware
is properly reset. After the first battery connection, a short power-on reset of 1 ms is
provided after voltage V1 is present. Once started, the microcontroller can set the Reset
Length Control (RLC) bit within the System Configuration register; this allows the reset
pulse to be adjusted for future reset events. With this bit set, all reset events are
lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms)
in Restart mode or Fail-safe mode. With this mechanism it is guaranteed that an
erroneously shortened reset pulse will restart any microcontroller, at least within the
second trial by using the long reset pulse.
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RSTN; the global ECU system reset
EN; a fail-safe global enable signal
Power-on (first battery connection) or V
Low V1 supply
V1 current above threshold during Standby mode while watchdog OFF behavior is
selected
V3 is down due to short-circuit condition during Sleep mode
RSTN externally forced LOW, falling edge event
Successful preparation for Flash mode completed
Successful exit from Flash mode
Wake-up from Standby mode via pins CAN, LIN or WAKE if programmed accordingly,
or any wake-up event from Sleep mode
Wake-up event from Fail-safe mode
Watchdog trigger failures (too early, overflow, wrong code)
Illegal mode code via SPI applied
Interrupt not served within t
Rev. 07 — 25 February 2010
RSTN(INT)
High-speed CAN/LIN fail-safe system basis chip
BAT42
below power-on reset threshold voltage
thH(V1)
Figure
while the watchdog is OFF,
3:
UJA1065
© NXP B.V. 2010. All rights reserved.
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