ST92F150-EVAL STMicroelectronics, ST92F150-EVAL Datasheet - Page 61

• Manufacturer Part Number: ST92F150-EVAL
• Description: BOARD EVALUATION FOR ST9 SERIES
• Manufacturer: STMicroelectronics

Specifications of ST92F150-EVAL

• Processor To Be Evaluated: ST90158 and ST92F1x Daughter Board
• Interface Type: I2C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2905

3.5 PROTECTION STRATEGY
The protection bits are stored in the 4 locations
from 231FFCh to 231FFFh (see
All the available protections are forced active dur-
ing reset, then in the initialisation phase they are
read from the TestFlash.
The protections are stored in 2 Non Volatile Regis-
ters. Other 2 Non Volatile Registers can be used
as a password to re-enable test modes once they
have been disabled.
The protections can be programmed using the Set
Protection operation (see Control Registers para-
graph), that can be executed from all the internal
or external memories except the Flash or Test-
Flash itself.
The TestFlash area (230000h to 231F7Fh) is al-
ways protected against write access.
Figure 34. Protection Register Map
3.5.1 Non Volatile Registers
The 4 Non Volatile Registers used to store the pro-
tection bits for the different protection features are
one time programmable by the user.
Access to these registers is controlled by the pro-
tections related to the TestFlash. Since the code to
program the Protection Registers cannot be
fetched by the Flash or the TestFlash memories,
this means that, once the APRO or APBR bits in
the NVAPR register are programmed, it is no long-
er possible to modify any of the protection bits. For
this reason the NV Password, if needed, must be
set with the same Set Protection operation used to
program these bits. For the same reason it is
strongly advised to never program the WPBR bit in
the NVWPR register, as this will prevent any fur-
ther write access to the TestFlash, and conse-
quently to the Protection Registers.
ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
231FFCh
231FFDh
231FFEh
231FFFh
NVPWD0
NVWPR
NVPWD1
NVAPR
Figure
34).
NON VOLATILE ACCESS PROTECTION REG-
ISTER (NVAPR)
Address: 231FFCh - Read/Write
Delivery value: 1111 1111 (FFh)
Bit 7 = Reserved.
Bit 6 = APRO: FLASH access protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the Flash
address space (
instruction is fetched from the TestFlash or from
the Flash itself.
0: ROM protection on
1: ROM protection off
Bit 5 = APBR: TestFlash access protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the Test-
Flash, the OTP and the protection registers, un-
less the current instruction is fetched from the
TestFlash or the OTP area.
0: TestFlash protection on
1: TestFlash protection off
Bit 4 = APEE:
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the
address space, unless the current instruction is
fetched from the TestFlash or from the Flash, or
from the
0:
1:
Bit 3 = APEX: Access Protection from External
memory.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the ad-
dress space of one of the internal memories (Test-
Flash, Flash,
is fetched from an external memory.
0: Protection from external memory on
1: Protection from external memory off
E
E
7
1
3 TM
3 TM
APRO APBR APEE APEX PWT2 PWT1 PWT0
protection on
protection off
6
E
3 TM
E
E
itself.
3 TM
5
E
3 TM
3 TM
, RAM), if the current instruction
access protection.
4
excluded), unless the current
3
2
1
61/429
E
0
3 TM
9