ST92F150-EVAL STMicroelectronics, ST92F150-EVAL Datasheet - Page 268
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ST92F150-EVAL
Manufacturer Part Number
ST92F150-EVAL
Description
BOARD EVALUATION FOR ST9 SERIES
Manufacturer
STMicroelectronics
Specifications of ST92F150-EVAL
Processor To Be Evaluated
ST90158 and ST92F1x Daughter Board
Interface Type
I2C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-2905
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I2C BUS INTERFACE
I
Figure 128. Transfer Sequencing
10-bit Master transmitter
Legend:
S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
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9
2
7-bit Slave receiver:
7-bit Slave transmitter:
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
10-bit Slave transmitter:
10-bit Master receiver:
S Address
S Address
S Header
S
S
S
C BUS INTERFACE (Cont’d)
EV5
EV5
EV5
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register or when DMA
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register or when DMA
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register, BTF is cleared by releasing the
lines (STOP=1, STOP=0) or writing DR register (for example DR=FFh). Note: If lines are released by
STOP=1, STOP=0 the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
Address
Address
Header
is complete.
is complete.
A
A
A
EV1
EV1 EV3
Address
A
A
A
Data1
EV6
EV6 EV8
EV9
A
Data1
Address
S
Data1
S
r
r
EV1
EV5
A
Header A
Data1
EV2
Data1
A
Header
A
A
Data2
EV3
EV7
EV6 EV8
A
EV1 EV3
A
Data2
EV8
A
Data2
EV2
EV6
A
Data2
Data1
EV2
Data1
A
.....
A
Data1
EV3
EV7
DataN
.....
A
A
A
EV8
EV8
A
DataN
.....
.....
EV3
EV7
A
DataN
.....
.....
DataN
....
.
EV2
.....
A
DataN
DataN
DataN
EV2
P
NA
NA
DataN
EV4
A
P
EV3-1
EV7
A
A
EV3-1
EV4
A
EV8
EV8
P
P
EV7
P
EV4
P
P
EV4
P
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