ST92F150-EVAL STMicroelectronics, ST92F150-EVAL Datasheet - Page 423

• Manufacturer Part Number: ST92F150-EVAL
• Description: BOARD EVALUATION FOR ST9 SERIES
• Manufacturer: STMicroelectronics

Specifications of ST92F150-EVAL

• Processor To Be Evaluated: ST90158 and ST92F1x Daughter Board
• Interface Type: I2C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2905

KNOWN LIMITATIONS (Cont’d)
13.8 EMULATION CHIP LIMITATIONS
Additional limitations exist on Emulation chips (EMU2 emulator). These limitations correspond to those
present in AxxxxxxxxY trace codes (ST92F150). They are listed in the following table.
13.8.1
DIRECTIONAL, WEAK PULL-UP PORTS
This section applies to ports P1[7:3], P4[1], P8[7:2]
and P9[7:0].
During the reset phase (external reset signal low)
and the delay of 20400 clock periods (t
lowing a reset, these ports are in High Impedance
state, while according to the datasheet they should
Table 76. Reset Behaviour Table
Shaded areas represent erroneous operations.
Section 13.8.1
Section 13.8.2
Section 13.8.3
Section 13.8.4
Section 13.8.5
Section 13.8.6
Section 13.8.7
Section 13.8.8
Section 13.8.9
Section 13.8.10
Section 13.8.11
P1[7:3] Bi-Dir + WPU
P8[7:2] Bi-Dir + WPU
P9[7:0] Bi-Dir + WPU
P4.1
Port
Section
RESET
Bi-Dir + WPU
Datasheet
Condition
RESET BEHAVIOUR FOR BI-DIRECTIONAL, WEAK PULL-UP PORTS
HIGH DRIVE I/Os WHEN BSZ=1
ADC PARASITIC DIODE
ADC ACCURACY VS. NEGATIVE INJECTION CURRENT
I2CECCR REGISTER LIMITATION
I2C BEHAVIOUR DISTURBED DURING DMA TRANSACTIONS
MFT DMA MASK BIT RESET
DMA DATA CORRUPTED BY MFT INPUT CAPTURE
SCI-A WRONG BREAK DURATION
LIN MASTER MODE NOT PRESENT ON SCI-A
LIMITATIONS ON LQFP64 PACKAGES
BEHAVIOUR
While RESET
is low
Hi-Z
Hi-Z
Hi-Z
Hi-Z
FOR
RSPH
Port Behaviour
During next
Limitation (AxxxxxxxxY trace code)
20K Clock
) fol-
Cycles
BI-
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ST92F124/F150/F250 - KNOWN LIMITATIONS
have weak pull-ups. These ports then enter Weak
Pull-up state until the user overwrites the reset
values of I/O Port Control Registers PxC0, PxC1
and PxC2.
Rev Z Behaviour
Bi-Dir + WPU
Bi-Dir + WPU
Bi-Dir + WPU
Bi-Dir + WPU
After these
20K Clock
Cycles
PxC0
Control Register Value
0
0
0
0
PxC1
0
0
0
0
PxC2
423/429
0
0
0
0
1