ST92F150-EVAL STMicroelectronics, ST92F150-EVAL Datasheet - Page 223

• Manufacturer Part Number: ST92F150-EVAL
• Description: BOARD EVALUATION FOR ST9 SERIES
• Manufacturer: STMicroelectronics

Specifications of ST92F150-EVAL

• Processor To Be Evaluated: ST90158 and ST92F1x Daughter Board
• Interface Type: I2C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2905

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.10 Interrupts and DMA
10.5.10.1 Interrupts
The SCI can generate interrupts as a result of sev-
eral conditions. Receiver interrupts include data
pending, receive errors (overrun, framing and par-
ity), as well as address or break pending. Trans-
mitter interrupts are software selectable for either
Transmit Buffer Register Empty (BSN set) or for
Transmit Shift Register Empty (BSN reset) condi-
tions.
Typical usage of the Interrupts generated by the
SCI peripheral are illustrated in
The SCI peripheral is able to generate interrupt re-
quests as a result of a number of events, several
of which share the same interrupt vector. It is
therefore necessary to poll S_ISR, the Interrupt
Status Register, in order to determine the active
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
Figure
116.
trigger. These bits should be reset by the program-
mer during the Interrupt Service routine.
The four major levels of interrupt are encoded in
hardware to provide two bits of the interrupt vector
register, allowing the position of the block of point-
er vectors to be resolved to an 8 byte block size.
The SCI interrupts have an internal priority struc-
ture in order to resolve simultaneous events. Refer
also to Section 10.5.4 SCI-M Operating Modes for
more details relating to Synchronous mode.
Table 47. SCI Interrupt Internal Priority
Receive DMA Request
Transmit DMA Request
Receive Interrupt
Transmit Interrupt
Highest Priority
Lowest Priority
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