ST92F150-EVAL STMicroelectronics, ST92F150-EVAL Datasheet - Page 239
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ST92F150-EVAL
Manufacturer Part Number
ST92F150-EVAL
Description
BOARD EVALUATION FOR ST9 SERIES
Manufacturer
STMicroelectronics
Specifications of ST92F150-EVAL
Processor To Be Evaluated
ST90158 and ST92F1x Daughter Board
Interface Type
I2C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-2905
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in
registers:
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
– A baud rate register (SCIBRR)
– An extended prescaler receiver register (SCIER-
– An extended prescaler transmitter register (SCI-
Refer to the register descriptions in
for the definitions of each bit.
Figure 118. Word Length Programming
PR)
ETPR)
9-bit Word length (M bit is set)
Figure
Start
Bit
8-bit Word length (M bit is reset)
Start
Bit
Bit0
117. It contains 6 dedicated
Bit0
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
Bit1
Bit1
Break Frame
Data Frame
Idle Frame
Break Frame
Data Frame
Idle Frame
Bit2
Bit2
Section 10.6.5
Bit3
Bit3
Bit4
Bit4
Bit5
Bit5
10.6.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Bit6
Bit6
Possible
Figure
Bit7
Parity
Bit7
Bit
Possible
Parity
Bit8
Bit
117).
Stop
Bit
Stop
Bit
Extra
Start
Next
Start
Bit
Bit
’1’
Extra
Next Data Frame
Next
Start
Start
Bit
Bit
’1’
Start
Bit
Next Data Frame
Start
Bit
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