ST92F150-EVAL STMicroelectronics, ST92F150-EVAL Datasheet - Page 414

• Manufacturer Part Number: ST92F150-EVAL
• Description: BOARD EVALUATION FOR ST9 SERIES
• Manufacturer: STMicroelectronics

Specifications of ST92F150-EVAL

• Processor To Be Evaluated: ST90158 and ST92F1x Daughter Board
• Interface Type: I2C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2905

ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
13.6 CAN FIFO CORRUPTION WHEN 2 FIFO MESSAGES ARE PENDING
Description
Under certain conditions, FIFO corruption can
occur in the following cases:
WHEN a bxCAN RX FIFO already holds 2 mes-
sages (i.e. FMP==2)
Figure 2. FIFO Corruption
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1
and Receive Message D
AND the application releases the same FIFO
Receive Message C
Release Message A
Release Message B
Release Message C
Release Message E
Release Message B
Receive Message A
Receive Message B
Receive Message E
(with the instruction CANx_CTRL_CRFRy |=
CRF_rfom;
x=0 for the CAN_0 cell
x=1 for the CAN_1 cell
y=0 for the Receive FIFO 0
y=1 for the Receive FIFO 1 )
* pointer to next receive location
v pointer to next message to be released
Initial State
FMP
0
1
2
3
2
2
3
2
1
0
v
E B C
v
v
v
A B C
E B C
E B C
* v
- - -
A - -
A B -
A B C
D B C
D B C
E B C
*
FIFO
*
*
v
* v
*
*
* v
v
*
*
*
v
v
When the FIFO is empty, v and * point to the same location
E released instead of B
* does not move because FIFO is full (normal operation)
D is overwritten by E
C released
* and v are not pointing to the same message
the FIFO is empty
* Does not move, pointer curruption
Normal operation
WHILE the bxCAN requests the transfer of a new
receive message into the FIFO (this lasts one CPU
cycle)
Impact on Application:
As the FIFO pointer is not updated correctly, this
causes the last message received to be over-
written by any incoming message. This means one
message is lost as shown in the example in
2
until a device reset occurs.
The bxCAN will not recover normal operation
THEN the internal FIFO pointer is not updated
BUT the FMP bits are updated correctly
Figure