AD9549/PCBZ Analog Devices Inc, AD9549/PCBZ Datasheet - Page 13

• Manufacturer Part Number: AD9549/PCBZ
• Description: BOARD EVALUATION FOR AD9549
• Manufacturer: Analog Devices Inc

Specifications of AD9549/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9549
• Primary Attributes: 2 Inputs, 2 Outputs, VCO
• Secondary Attributes: CMOS, HSTL Output Logic, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, AVDD, AVDD3, and DVDD are at nominal supply voltage; f
(SYSCLK PLL Enabled Driven by R&S SMA100 Signal Generator at 50 MHz),
Figure 3. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
Figure 4. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
Figure 5. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
–70
–80
–90
–70
–80
–90
–70
–80
–90
(SYSCLK PLL Bypassed), f
f
REF
10
10
10
DPLL Loop BW = 1 kHz, HSTL Output Doubler Enabled
= 19.44 MHz, f
100
f
100
100
(SYSCLK PLL Bypassed), f
OUT
= 311.04 MHz, DPLL Loop BW = 1 kHz
1k
1k
1k
OUT
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
= 311.04 MHz, DPLL Loop BW = 1 kHz
RMS JITTER (12kHz TO 20MHz): 0.36ps
RMS JITTER (50kHz TO 80MHz): 0.42ps
RMS JITTER (12kHz TO 20MHz): 0.18ps
RMS JITTER (50kHz TO 80MHz): 0.24ps
RMS JITTER (12kHz TO 20MHz): 1.01ps
RMS JITTER (50kHz TO 80MHz): 1.04ps
REF
10k
10k
10k
= 19.44 MHz, f
100k
100k
100k
REF
= 19.44 MHz,
OUT
1M
1M
1M
= 622.08 MHz,
10M
10M
10M
100M
100M
100M
Rev. D | Page 13 of 76
(SYSCLK PLL Enabled and Driven by R&S SMA100 at 50 MHz), f
Figure 6. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
Figure 7. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
Figure 8. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by R&S SMA100 Signal Generator at
(SYSCLK PLL Enabled and Driven by R&S SMA100 Signal Generator at
50 MHz), f
f
OUT
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
50 MHz), f
–70
–80
–90
–70
–80
–90
–70
–80
–90
= 155.52 MHz, SYSCLK Doubler Enabled, DPLL Loop BW =1 kHz
10
10
10
System Clock Doubler Enabled, HSTL Doubler Enabled
S
REF
= 1 GHz, DAC R
= 19.44 MHz, f
REF
100
100
100
= 8 kHz, f
1k
1k
1k
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
OUT
RMS JITTER (12kHz TO 20MHz): 1.09ps
RMS JITTER (50kHz TO 80MHz): 1.14ps
RMS JITTER (12kHz TO 20MHz): 1.07ps
RMS JITTER (50kHz TO 80MHz): 1.16ps
OUT
RMS JITTER (12kHz TO 20MHz): 1.0ps
RMS JITTER (50kHz TO 80MHz): 1.2ps
= 155.52 MHz, DPLL Loop BW = 10 Hz
10k
10k
10k
= 622.08 MHz, DPLL Loop BW = 1 kHz,
SET
= 10 kΩ.
100k
100k
100k
1M
1M
1M
10M
10M
10M
REF
AD9549
= 19.44 MHz,
100M
100M
100M