AD9549/PCBZ Analog Devices Inc, AD9549/PCBZ Datasheet - Page 53

• Manufacturer Part Number: AD9549/PCBZ
• Description: BOARD EVALUATION FOR AD9549
• Manufacturer: Analog Devices Inc

Specifications of AD9549/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9549
• Primary Attributes: 2 Inputs, 2 Outputs, VCO
• Secondary Attributes: CMOS, HSTL Output Logic, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O REGISTER DESCRIPTIONS
SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005)
Register 0x0000—Serial Configuration
Table 14.
Bits
[7:4]
3
2
1
0
Register 0x0001—Reserved
Register 0x0002 and Register 0x0003—Part ID (Read Only)
Register 0x0004—Serial Options
Table 15.
Bits
0
Register 0x0005—Serial Options (Self-Clearing)
Table 16.
Bits
0
POWER-DOWN AND RESET (REGISTER 0x0010 TO REGISTER 0x0013)
Register 0x0010—Power-Down and Enable
Power-up default is defined by the startup pins.
Table 17.
Bits
7
6
5
4
3
2
1
0
Bit Name
Long instruction
Soft reset
LSB first
SDO active
Bit Name
Read buffer register
Bit Name
Register update
Bit Name
PD HSTL driver
Enable CMOS driver
Enable output doubler
PD SYSCLK PLL
PD REFA
PD REFB
Full PD
Digital PD
Description
Power down HSTL output driver.
1 = HSTL driver powered down.
Power up CMOS output driver.
1 = CMOS driver on.
Power up output clock generator doubler. Output doubler must still be enabled in Register 0200.
System clock multiplier power-down.
1 = system clock multiplier powered down.
Power-down reference clock A input (and related circuits).
Power-down reference clock B input (and related circuits).
Setting this bit is identical to activating the PD pin and puts all blocks (except serial port) into power-down
mode. SYSCLK is turned off.
Remove clock from most of digital section; leave serial port usable. In contrast to full PD, setting this bit
does not debias inputs, allowing for quick wake-up.
Description
These bits are the mirror image of Bits[3:0].
Read-only. The AD9549 supports only long instructions.
Resets register map, except for Register 0x0000. Setting this bit forces a soft reset, meaning that S1 to S4
are not tristated, nor is their state read when this bit is cleared. The AD9549 assumes the values of S1 to S4
that were present during the last hard reset. This bit is not self-clearing, and all other registers are restored
to their default values after a soft reset.
Sets bit order for serial port.
1 = LSB first.
0 = MSB first. I/O update must occur for MSB first to take effect.
Enables SDO pin.
1 = SDO pin enabled (4-wire serial port mode).
0 = 3-wire mode.
Description
For buffered registers, serial port readback reads from actual (active) registers instead of the buffer.
1 = reads the buffered values that take effect during the next I/O update.
0 = reads values that are currently in effect.
Description
Software access to the register update pin function. Writing a 1 to this bit is identical to performing an I/O
update.
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AD9549