C8051F040DK Silicon Laboratories Inc, C8051F040DK Datasheet - Page 215

• Manufacturer Part Number: C8051F040DK
• Description: DEV KIT FOR F040/F041/F042/F043
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F040DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F04x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F040
• Silicon Family Name: C8051F04x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F040, 041, 042, 043 MCUs
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1205

Bit7:
Bit6-4:
Bit3:
Bit2:
Bit1:
Bit0:
Bits7-0:
CTXOUT
R/W
P0.7
Bit7
R/W
Bit7
CTXOUT: CAN Transmit Pin (CTX) Output Mode.
0: CTX pin output mode is configured as open-drain.
1: CTX pin output mode is configured as push-pull.
Reserved
CP2E: CP2 Output Enable Bit.
0: CP2 unavailable at Port pin.
1: CP2 routed to Port pin.
CNVST2E: ADC2 External Convert Start Input Enable Bit (C8051F040/1/2/3 only).
0: CNVST2 for ADC2 unavailable at Port pin.
1: CNVST2 for ADC2 routed to Port pin.
T3EXE: T3EX Input Enable Bit.
0: T3EX unavailable at Port pin.
1: T3EX routed to Port pin.
T3E: T3 Input Enable Bit.
0: T3 unavailable at Port pin.
1: T3 routed to Port pin.
P0.[7:0]: Port0 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P0MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P0.n pin is logic low.
1: P0.n pin is logic high.
Note: P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) can be driven by the External Data Memory
Interface. See
page 187
ing the Crossbar for External Memory accesses.
SFR Definition 17.4. XBR3: Port I/O Crossbar Register 3
Bit6
P0.6
—
R/W
R
Bit6
for more information. See also SFR Definition 17.3 for information about configur-
Section “16. External Data Memory Interface and On-Chip XRAM” on
P0.5
Bit5
R/W
Bit5
—
R
SFR Definition 17.5. P0: Port0 Data
P0.4
R/W
Bit4
Bit4
—
R
Rev. 1.5
CP2E
P0.3
R/W
Bit3
R/W
Bit3
C8051F040/1/2/3/4/5/6/7
CNVST2E
P0.2
R/W
Bit2
R/W
Bit2
T3EXE
P0.1
R/W
Bit1
R/W
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P0.0
R/W
Bit0
T3E
R/W
Bit0
0x80
All Pages
Addressable
0xE4
F
Reset Value
00000000
11111111
Reset Value
Bit
215