C8051F040DK Silicon Laboratories Inc, C8051F040DK Datasheet - Page 212

DEV KIT FOR F040/F041/F042/F043

C8051F040DK

Manufacturer Part Number
C8051F040DK
Description
DEV KIT FOR F040/F041/F042/F043
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F040DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F04x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F040
Silicon Family Name
C8051F04x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F040, 041, 042, 043 MCUs
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1205

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F040DK
Manufacturer:
SiliconL
Quantity:
9
C8051F040/1/2/3/4/5/6/7
212
Bit7:
Bit6:
Bits5-3:
Bit2:
Bit1:
Bit0:
CP0E
R/W
Bit7
CP0E: Comparator 0 Output Enable Bit.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
ECI0E: PCA0 External Counter Input Enable Bit.
0: PCA0 External Counter Input unavailable at Port pin.
1: PCA0 External Counter Input (ECI0) routed to Port pin.
PCA0ME: PCA0 Module I/O Enable Bits.
000: All PCA0 I/O unavailable at port pins.
001: CEX0 routed to port pin.
010: CEX0, CEX1 routed to 2 port pins.
011: CEX0, CEX1, and CEX2 routed to 3 port pins.
100: CEX0, CEX1, CEX2, and CEX3 routed to 4 port pins.
101: CEX0, CEX1, CEX2, CEX3, and CEX4 routed to 5 port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, and CEX5 routed to 6 port pins.
UART0EN: UART0 I/O Enable Bit.
0: UART0 I/O unavailable at Port pins.
1: UART0 TX routed to P0.0, and RX routed to P0.1.
SPI0EN: SPI0 Bus I/O Enable Bit.
0: SPI0 I/O unavailable at Port pins.
1: SPI0 SCK, MISO, MOSI, and NSS routed to 4 Port pins. Note that the NSS signal is not
assigned to a port pin if the SPI is in 3-wire mode. See Section
Peripheral Interface
SMB0EN: SMBus0 Bus I/O Enable Bit.
0: SMBus0 I/O unavailable at Port pins.
1: SMBus0 SDA and SCL routed to 2 Port pins.
ECI0E
SFR Definition 17.1. XBR0: Port I/O Crossbar Register 0
R/W
Bit6
R/W
Bit5
(SPI0)” on page
PCA0ME
R/W
Bit4
Rev. 1.5
255
R/W
Bit3
for more information.
UART0EN SPI0EN
R/W
Bit2
R/W
Bit1
“20. Enhanced Serial
SFR Address:
SMB0EN 00000000
SFR Page:
R/W
Bit0
0xE1
F
Reset Value

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