MAX3420EEVKIT-2+ Maxim Integrated Products, MAX3420EEVKIT-2+ Datasheet - Page 4

• Manufacturer Part Number: MAX3420EEVKIT-2+
• Description: EVAL KIT FOR MAX3420E
• Manufacturer: Maxim Integrated Products

Specifications of MAX3420EEVKIT-2+

• Main Purpose: Interface, USB 2.0 Slave
• Embedded: No
• Utilized Ic / Part: MAX3420E
• Primary Attributes: Full Speed (12Mbps), SPI Interface, No Custom USB Drivers
• Secondary Attributes: 4 GPI Pushbuttons, 4 GPO LEDs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB Peripheral Controller
with SPI Interface
4
TQFN-EP
4, 14
_______________________________________________________________________________________
10
11
12
13
15
16
1
2
3
5
6
7
8
9
PIN
5, 6, 18, 19
LQFP
3, 4
10
11
12
13
14
15
17
20
21
1
2
7
8
GPOUT0
GPOUT1
GPOUT2
GPOUT3
NAME
SCLK
MOSI
MISO
GND
RES
GPX
INT
D+
SS
V
D-
L
OUTPUT
INPUT/
Input or
Output
Output
Output
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input
Input
Input
Input
Input
General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are
referenced to the voltage on V
states by writing to bit 3 through bit 0 of the IOPINS (R20) register.
Level-Translator Reference Voltage. Connect V
logic-level power supply. Bypass V
to the V
Ground
General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are
referenced to the voltage on V
states by writing to bit 3 through bit 0 of the IOPINS (R20) register.
Device Reset. Drive RES low to clear all of the internal registers except for
PINCTL (R17), USBCTL (R15), and SPI logic. See the Device Reset section for a
description of resets available on the MAX3420E. Note: The MAX3420E is
internally reset if either V
accessible under these conditions.
SPI Serial-Clock Input. An external SPI master supplies this clock with
frequencies up to 26MHz. The logic level is referenced to the voltage on V
Data is clocked into the SPI slave interface on the positive edge of SCLK. Data
is clocked out of the SPI slave interface on the falling edge of SCLK.
SPI Slave-Select Input. The SS logic level is referenced to the voltage on V
When SS is driven high, the SPI slave interface is not selected and SCLK
transitions are ignored. An SPI transfer begins with a high-to-low SS transition
and ends with a low-to-high SS transition.
SPI Serial-Data Output (Master-In, Slave-Out). MISO is a push-pull output. MISO
is tri-stated in half-duplex mode or when SS = 1. The MISO logic level is
referenced to the voltage on V
SPI Serial-Data Input (Master-Out, Slave-In). The logic level on MOSI is
referenced to the voltage on V
MOSI/MISO input and output.
General-Purpose Multiplexed Output. The internal MAX3420E signal that
appears on GPX is programmable by writing to the GPXB and GPXA bits of the
PINCTL (R17) register. GPX indicates one of four signals: OPERATE (00,
default), VBUS_DET (01), BUSACT (10), and SOF (11).
Interrupt Output. In edge mode, the logic level on INT is referenced to the
voltage
on VL. In edge mode, INT is a push-pull output with programmable polarity. In
level mode, INT is open-drain and active low. Set the IE bit in the CPUCTL
(R16) register to enable INT.
USB D- Signal. Connect D- to a USB “B” connector through a 33
resistor.
USB D+ Signal. Connect D+ to a USB “B” connector through a 33
resistor. The 1.5k
L
pin as possible.
D+ pullup resistor is internal to the device.
CC
of V
L
L
L
L
. The SPI master controls the GPOUT3–GPOUT0
. The SPI master controls the GPOUT3–GPOUT0
.
. MOSI can also be configured as a bidirectional
L
is not present. The register file is not
FUNCTION
L
to ground with a 0.1μF capacitor as close
L
to the system’s 1.71V to 3.6V
Pin Description
±1% series
±1% series
L
L
.
.