MAX3420EEVKIT-2+ Maxim Integrated Products, MAX3420EEVKIT-2+ Datasheet - Page 17

• Manufacturer Part Number: MAX3420EEVKIT-2+
• Description: EVAL KIT FOR MAX3420E
• Manufacturer: Maxim Integrated Products

Specifications of MAX3420EEVKIT-2+

• Main Purpose: Interface, USB 2.0 Slave
• Embedded: No
• Utilized Ic / Part: MAX3420E
• Primary Attributes: Full Speed (12Mbps), SPI Interface, No Custom USB Drivers
• Secondary Attributes: 4 GPI Pushbuttons, 4 GPO LEDs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 15. SPI Port in Full-Duplex Mode
(5) To write SPI data, the SPI master keeps its output
(6) The SPI master terminates the SPI cycle by return-
Figures 8 and 9 show timing diagrams for full- and half-
duplex operation.
The serial-interface engine (SIE) does most of the
detailed work required by USB protocol:
An internal PLL multiplies the 12MHz oscillator signal
by four to produce an internal 48MHz clock. When the
chip is powered down, the oscillator is turned off to
conserve power. When repowered, the oscillator and
PLL require time to stabilize and lock. The OSCOKIRQ
interrupt bit is used to indicate to the SPI master that
the clocking system is stable and ready for operation.
• USB packet PID detection and checking
• CRC check and generation
• Automatic retries in case of errors
• USB packet generation
• NRZI data encoding and decoding
• Bit stuffing and unstuffing
• Various USB error condition detection
• USB bus reset, suspend, and wake-up detection
• USB resume signaling
• Automatic flow control (NAK)
driver on and clocks subsequent bytes into the
MOSI pin. To read SPI data, after the eighth clock
cycle the SPI master tri-states its output driver and
begins clocking in data bytes from the MOSI pin.
ing SS high.
MISO
SCLK
MOSI
SS
______________________________________________________________________________________
USB Serial-Interface Engine
SUSPIRQ
REG4
URESIRQ
REG3
SUDAVIRQ
REG2
SPI MODE 0,0 (CPOL = 0, CPHA = 0)
IN3BAVIRQ
REG1
PLL
USB Peripheral Controller
IN2BAVIRQ
REG0
According to USB rev. 2.0 specification, when a USB
host stops sending traffic for at least 3 milliseconds to a
peripheral, the peripheral must enter a power-down
state called SUSPEND. Once suspended, the peripher-
al must have enough of its internal logic active to rec-
ognize when the host resumes signaling, or if enabled
for remote wakeup, that the SPI master wishes to signal
a resume event. The following sections titled Suspend
and Wakeup and USB Resume describe how the SPI
master coordinates with the MAX3420E to accomplish
this power management.
After three milliseconds of USB bus inactivity, a USB
peripheral is required to enter the USB suspend state
and draw no more than 500µA of supply current. To
accomplish this, after three milliseconds of USB bus
inactivity, the MAX3420E sets the SUSPIRQ bit in the
USBIRQ (R13) register and asserts the INT output, if
SUSPIE = 1 and IE = 1. The SPI master must do any
necessary power-saving housekeeping and then set
the PWRDOWN bit in the USBCTL (R15) register. This
instructs the MAX3420E to enter a power-down state, in
which it does the following:
Note that the MAX3420E does not automatically enter
a power-down state after three milliseconds of bus
inactivity. This allows the SPI master to perform any
• Stops the 12MHz oscillator
• Keeps the INT output active (according to the
• Monitors the USB D+ line for bus activity
• Monitors the SPI port for any traffic
mode set in the PINCTL (R17) register)
OUT1DAVIRQ OUT0DAVIRQ
0
with SPI Interface
DIR
IN0BAVIRQ
Power Management
ACKSTAT
X
Suspend
17