LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 91

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

Register
Address
16.13.25 Register E2h LM96194 Status Control
E2h
Read/
Write
R/W
Lock
X
LM96194
Register
Control
Status/
Name
Bit
5:4
0
1
2
3
6
7
TACH_EDGE
HOST_ERR
BMC_ERR
GP15_AM
GPI4_AM
OVRID
Name
_ERR
ASF
BMC
Bit 7
TACH_EDGE
0h
1h
2h
3h
HOST
_ERR
Bit 6
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Bit 5
TACH_EDGE
If this bit is set, all PWM outputs go to 100% duty cycle.
If this bit is set, BMC error registers support ASF, i.e.
reset on read. When not in ASF mode, a write “1” is
required to clear the bits in the BMC error status
registers.
GPI4 Auto Mask Enable
If this bit is set, an error event on GPI4 causes all other
error events to be masked.
The BMC Error Status registers do not reflect any new
error events until the GPI4_ERR bit is cleared in the
B_GPI Error Status register. The HOST Error Status
registers do not reflect any new error events until the
GPI4_ERR bit is cleared in the H_GPI Error Status
register.
If a CPU_THERMTRIP signal is connected to GPIO4,
this ensures that unwanted error events do not fire once
CPU_THERMTRIP is asserted.
GPI5 Auto Mask Enable
This bit works exactly the same as GPI4_AM, but applies
to GPI5.
This field determines what type of edges are used for
measuring fan tach pulses. This effects all four
tachometer inputs.
This bit gets set if any error bit is set in any of the Host
Error Status registers (H_).
This bit gets set if any error bit is set in any of the BMC
Error Status registers (B_). When this bit is set, ALERT
are asserted if enabled.
Either rising or falling edges may
be used.
Rising edges only
Falling edges only
Reserved
91
Tachometer Measurements
Bit 4
Edge Type Used for
GPI5_A
Bit 3
M
Description
GPI4_AM
Bit 2
Bit 1
ASF
OVRID
Bit 0
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Default
Value
00h