LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 18

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

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13.5 GPIO and GPI PINS
The LM96194 has 8 GPIO pins than can act as either as gen-
eral purpose inputs or outputs and 1 GPI pin that can act as
general purpose input. Each can be configured and controlled
independently. When acting as an input the pin can be
masked to prevent it from setting a corresponding bit in the
GPI Error status registers. Some of these pins can also func-
tion as tachometer or VID inputs.
13.6 FAN TACH INPUTS
The fan inputs are Schmitt-Trigger digital inputs. Schmitt-
Trigger input circuitry is included to accommodate slow rise
and fall times typical of fan tachometer outputs.
The maximum input signal range is 0V to +6.0V, even when
V
from fan outputs, which exceed 0V to +6.0V, either resistive
attenuation of the fan signal or diode clamping must be in-
cluded to keep inputs within an acceptable range, thereby
preventing damage to the LM96194.
Hot plugging fans can involve spikes on the Tach signals of
up to 12V so diode protection or other circuitry is required. For
“Hot Plug” fans, external clamp diodes may be required for
signal conditioning.
14.0 SMBus Interface
The SMBus is used to communicate with the LM96194.
LM96194 SMBus interface lines are designed to be tolerant
to 5V signalling. Necessary pull-ups are located on the base-
board. Care should be taken to ensure that only one pull-up
is used for each SMBus signal. The SMBus interface obeys
the SMBus 2.0 protocols and signaling levels.
The SMBus interface of the LM96194 does not load down the
SMBus if no power is applied to the LM96194. This allows a
module containing the LM96194 to be powered down and re-
placed, if necessary.
14.1 SMBus ADDRESSING
Each time the LM96194 is powered up, it latches the assigned
SMBus slave address (determined by ADDR_SEL) during the
first valid SMBus transaction in which the first five bits of the
targeted slave address match those of the LM96194 slave
address. Once the address has been latched, the LM96194
continues to use that address for all future transactions until
power is lost.
The address select input detects three different voltage levels
and allows for up to 3 devices to exist in a system. The ad-
dress assignment is as follows:
14.2 DIGITAL NOISE EFFECT ON SMBus
COMMUNICATION
Noise coupling into the digital lines (greater than 150mV),
overshoot greater than V
may prevent successful SMBus communication with the
LM96194. SMBus No Acknowledge (NACK) is the most com-
mon symptom, causing unnecessary traffic on the bus. Al-
though, the SMBus maximum frequency of communication is
rather low (100 kHz max), care still needs to be taken to en-
sure proper termination within a system with multiple parts on
the bus and long printed circuit board traces. The LM96194
DD
is less than 5V. In the event that these inputs are supplied
Address Select Pin
(ADDR_SEL)
V
High
Low
DD
/2
DD
and undershoot less than GND,
Slave Address
Assignment
01011 01
01011 10
01011 00
18
includes on chip low-pass filtering of the SMBCLK and SMB-
DAT signals to make it more noise immune. Minimize noise
coupling by keeping digital traces out of switching baseboard
areas as well as ensuring that digital lines containing high
speed data communications cross at right angles to the SMB-
DAT and SMBCLK lines.
14.3 GENERAL SMBus TIMING
The SMBus 2.0 specification defines specific conditions for
different types of read and write operations but in general the
SMBus protocol operates as follows:
The master initiates data transfer by establishing a START
condition, defined as a high to low transition on the serial data
line SMBDAT while the serial clock line SMBCLK remains
high. This indicates that a data stream follows. All slave pe-
ripherals connected to the serial bus respond to the START
condition, and shift in the next 8 bits. This consists of a 7-bit
slave address (MSB first) plus a R/W bit, which determines
the direction of the data transfer, i.e. whether data is written
to or read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit, and holding it low during the high period of this clock
pulse. All other devices on the bus now remain idle while the
selected device waits for data to be read from or written to it.
If the R/W bit is a 0 then the master writes to the slave device.
If the R/W bit is a 1 the master reads from the slave device.
Data is sent over the serial bus in sequences of 9 clock puls-
es, 8 bits of data followed by an Acknowledge bit. Data
transitions on the data line must occur during the low period
of the clock signal and remain stable during the high period,
as a low to high transition when the clock is high may be in-
terpreted as a STOP signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave de-
vice what to expect next. It may be an instruction, such as
telling the slave device to expect a block write, or it may simply
be a register address that tells the slave where subsequent
data is to be written.
Since data can flow in only one direction as defined by the R/
W bit, it is not possible to send a command to a slave device
during a read operation. Before doing a read operation, it is
necessary to do a write operation to tell the slave what sort of
read operation to expect and/or the address from which data
is to be read.
When all data bytes have been read or written, stop conditions
are established. In WRITE mode, the master will allow the
data line to go high during the 10th clock pulse to assert a
STOP condition. In READ mode, the slave drives the data not
the master. For the bit in question, the slave is looking for an
acknowledge and the master doesn't drive low. This is known
as ‘No Acknowledge’. The master then takes the data line low
during the low period before the 10th clock pulse, then high
during the 10th clock pulse to assert a STOP condition.
Note, a repeated START may be given only between a write
and read operation that are in succession.
14.4 SMBus ERROR SAFETY FEATURES
To provide a more robust SMBus interface, the LM96194 in-
corporates a timeout feature for both SMBCLK and
SMBDAT. If either signal is low for a long period of time (see
SMBus AC specs), the LM96194 SMBus state machine re-
verts to the idle state and waits for a START signal. Large
block transfers of all zeros should be avoided if the SMBCLK
is operating at a very low frequency to avoid accidental time-