LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 6

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

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Symbol
RESET
AGND
REMOTE1−
REMOTE1a+
REMOTE2−
REMOTE2a+
AD_IN1/REMOTE1b+
AD_IN2/REMOTE2b+
AD_IN3
AD_IN4 (Vccp)
AD_IN5
GND
GND
GND
Pin #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Type
Digital I/O (Open-
Drain)
GROUND Input
Remote Thermal
Diode_1- Input (CPU
THERMDC)
Remote Thermal
Diode_1a+ I/O (CPU
THERMDA1)
Remote Thermal
Diode_2 - Input
Remote Thermal
Diode_2a + I/O
Analog Input (+12V1 or
CPU1 THERMDA2)
Analog Input or
Remote Thermal
Diode_2b + I/O
Analog Input (+12V3)
Analog Input
(CPU1_Vccp)
Analog Input (+3.3V)
Ground
Ground
Ground
Function
Open-drain reset output when power is first applied to the LM96194. Used
as a reset for devices powered by 3.3V stand-by. After reset, this pin
becomes a reset input. See Section (TBD) for more information. If this pin
is not used, connection to an external resistive pull-up is required to prevent
LM96194 malfunction.
Analog Ground. All grounds need to be tied together at the chip then taken
to a low noise system ground. A voltage difference between grounds may
cause erroneous results.
This is the negative input (current sink) from both of the CPU thermal
diodes. Connected to THERMDC pin of Pentium processor or the emitter
of a diode connected MMBT3904 NPN transistor. Serves as the negative
input into the A/D for thermal diode voltage measurements. A 100 pF
capacitor is optional and can be connected between REMOTE1− and
REMOTE1+.
This is a positive connection to the first CPU thermal diode. Serves as the
positive input into the A/D for thermal diode voltage measurements. It also
serves as a current source output that forward biases the thermal diode.
Connected to THERMDA pin of Pentium processor or the base of a diode
connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and
can be connected between REMOTE1− and each REMOTE1+.
This is the negative input (current sink) from both of the CPU2 thermal
diodes. Connected to THERMDC pins of Pentium processor or the emitter
of a diode connected MMBT3904 NPN transistor. Serves as the negative
input into the A/D for thermal diode voltage measurements. A 100 pF
capacitor is optional and can be connected between REMOTE2− and each
REMOTE2+.
This is a positive connection to the third thermal diode. Serves as the
positive input into the A/D for thermal diode voltage measurements. It also
serves as a current source output that forward biases the thermal diode.
Connected to THERMDA pin of Pentium processor or the base of a diode
connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and
can be connected between REMOTE2− and REMOTE2+.
Analog Input for +12V Rail 1 monitoring, for CPU1 voltage regulator.
External attenuation resistors required such that 12V is attenuated to
0.927V for nominal ¾ scale reading. This pin may also serve as the second
positive thermal diode input for the CPU.
Analog Input for +12V Rail 2 monitoring. External attenuation resistors
required such that 12V is attenuated to 0.927V for nominal ¾ scale reading.
This pin may also serve as the fourth positive thermal diode input.
Analog Input for +12V Rail 3, for Memory/3GIO slots. External attenuation
resistors required such that 12V is attenuated to 0.927V for nominal ¾ scale
reading.
Analog input for +Vccp (processor voltage) monitoring.
Analog input for +3.3V monitoring, nominal ¾ scale reading
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
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