LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 90

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

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Register
Address
Register
Address
16.13.23 Register E0h Special Function TACH to PWM Binding
If a TACH channel is bound to a PWM channel, TACH errors on that channel are automatically masked when the bound PWM is
at 0% duty cycle or performing spin-up. Behavior is undefined if a TACH channel is bound to both PWM outputs. This register must
be setup when Smart Tach Mode is enabled in register BDh, Special Function Control 2, and when Tach Boost is enabled in register
E1h, Tachometer Fan Boost Cotrol.
16.13.24 Register E1h Tachometer Fan Boost Control Register
E1h
Lock
E0h
X
Read/
Write
R/W
Read/
Write
R/W
Bit
5:0
6
7
Bit
Tach Fan Boost Control
0
1
2
3
4
5
6
7
Register Name
Special Function
TACH to PWM
TBT[5:0]
Register
Binding
Name
60
61
62
63
Name
T1P1
T1P2
T2P1
T2P2
T3P1
T3P2
T4P1
T4P2
N
0
1
·
·
·
TBT[5:0]]
Name
TBS
RES
Timeout Assignments for TBT[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T4P2
Bit 7
Bit 7
RES
If set, TACH1 is bound to PWM1.
If set, TACH1 is bound to PWM2.
If set, TACH2 is bound to PWM1.
If set, TACH2 is bound to PWM2.
If set, TACH3 is bound to PWM1.
If set, TACH3 is bound to PWM2.
If set, TACH4 is bound to PWM1.
If set, TACH4 is bound to PWM2.
R/W
R/W
R/W
R
T4P1
Bit 6
Bit 6
TBS
90
Description
TACH error fan boost enable timeout. Set to 63 (3Fh) to disable the
TACH error fan boost feature (default). Values other than 63 enable
the TACH error fan boost feature and set the timeout according to
the following table.
TACH boost status: When set, this bit indicates that the TACH error
boost has been triggered and is currently requesting 100% PWM.
If bits [5:0] are configured for an infinite timeout, and the TACH error
(s) have ceased, then writing a zero to this bit will un-trigger the
TACH boost. If TACH error boost is disabled, this bit always returns
a 0.
Reserved
Infinite setting (software must clear bit 6 of this register to reset)
T3P2
Bit 5
Bit 5
T3P1
Bit 4
Description
Bit 4
T2P2
Bit 3
Bit 3
Timeout/Function
N * 32 * 0.091 sec
TBT[5:0]
Disabled
T2P1
Bit 2
175
178
0
3
Bit 2
·
·
·
T1P2
Bit 1
Bit 1
T1P1
Bit 0
Bit 0
Default
Value
Default
00h
Value
3Fh