LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 42

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

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Register
Address
Register
Address
Register
Address
Register
Address
Register
Address
These bits set the upper 8-bits of the 9-bit override duty cycle value for PWM1.
16.5.3 Register 0Eh PWM2 Duty Cycle Override (low byte)
If manual PWM 2 override is enabled in this register, all other PWM 2 bindings are disabled except for the 100% override in the
LM96194 Status Control register (E2h).
16.5.4 Register 0Fh PWM2 Duty Cycle Override (high byte)
These bits set the upper 8-bits of the 9-bit override duty cycle value for PWM2.
16.6 EXTENDED RESOLUTION VALUE REGISTERS
16.6.1 Registers 10h - 17h Zone 1 (CPU) and Zone 2 (MMBT3904) Extended Resolution Unfiltered Temperature Value
Registers, Most and Least Significant Bytes
Register 11h is a mirror of register Zone 1a (CPU) Temp at address 50h.
Register 13h is a mirror of register Zone 1b (CPU) Temp at address 06h.
Register 15h is a mirror of register Zone 2a (MMBT3904) Temp at address 51h.
0Eh
0Fh
10h
11h
12h
13h
14h
15h
5:0
Bit
6
7
Read/
Read/
Write
Write
Read/
Read/
Read/
R/W
R/W
Write
Write
Write
R
R
R
R
R
R
PWM2_EN_Hres_Over
PWM 2 Duty Cycle
Override (low byte)
PWM2 Duty Cycle
PWM2_DC[0]
Register Name
Register Name
Override (high
Z1a_MSB
Z1b_MSB
Z2a_MSB
Z1a_LSB
Z1b_LSB
Z2a_LSB
Register
Register
Register
Name
Name
Name
Name
RES
byte)
Bit 7
Bit 7
Bit 7
Sign
Sign
Sign
0.5
0.5
0.5
PWM2_
DC[0]
Bit 7
Bit 7
Bit 6
Bit 6
Bit 6
R/W
R/W
R/W
64
64
64
R
0
0
0
PWM2_
EN_Hre
_Over
Bit 6
Bit 6
s
Description
Reserved
When this bit is set, high-resolution override for PWM2 is enabled. When
this bit is set, PWM2 will run at the programmed duty cycle: PWM2_DC
[8:0]/256 * 100%; values over 100h are reserved.
When this bit is set, bit [0] of the override duty cycle for PWM2 is set.
Bit 5
Bit 5
Bit 5
32
32
32
0
0
0
Bit 5
Bit 5
RES
42
Bit 4
Bit 4
Bit 4
16
16
16
0
0
0
PWM2_DC[8:1]
Bit 4
Bit 4
RES
Bit 3
Bit 3
Bit 3
0
8
0
8
0
8
Bit 3
Bit 3
RES
Bit 2
Bit 2
Bit 2
0
4
0
4
0
4
Bit 2
Bit 2
RES
Bit 1
Bit 1
Bit 1
0
2
0
2
0
2
Bit 1
Bit 1
RES
Bit 0
Bit 0
Bit 0
0
1
0
1
0
1
Bit 0
Bit 0
RES
Default
Default
Default
Value
Value
Value
Default
Default
Value
Value
00h
00h
00h
00h
00h
00h
00h
00h