LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 24

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

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Special Notes:
1.
2.
3.
4.
5.
6.
14.5.4.5 SMBus Fixed Address Block Reads
Block reads can be performed from pre-defined addresses. A special command code has been reserved for each pre-defined
address. See the
of events that occur for this type of block read:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The master continues to receive data bytes and asserting an ACK.
11. The master receives the last data byte.
12. The master asserts a NACK.
13. The master issues a STOP to end this transaction.
Special Notes:
1.
2.
3.
4.
1
S
… Block
1
S
Steps 9 through 19 can be repeated to read another block of data. The address auto-increments such that the next block starts
where the last block left off. The size returned by the LM96194 is the same each time.
The LM96194 returns 00h when address locations outside of normal address space are read.
Block reads do not wrap around from address FFh to 00h
If the master acknowledges more bytes that it requested, the LM96194 continues to supply data until the master does not
acknowledge a byte.
If the master does not acknowledges a byte to prematurely abort a block read, the LM96194 gets off the bus to allow the
master to issue a STOP signal.
After a block read is finished, the base address of the LM96194 is updated to point to the byte just beyond the last byte read.
The master sends a START to start this transaction.
The master sends the 7-bit slave address followed by a write bit (low).
The slave asserts an ACK.
The master sends a Fixed Block Command Code (F2h-FDh) and the slave asserts an ACK.
The master sends a repeated START.
The master sends the 7-bit slave address followed by a read bit (high).
The slave asserts an ACK.
The master receives the Byte Count (depends on the Fixed Block Command Code used) and asserts an ACK.
The master receives the first data byte and asserts an ACK.
The LM96194 returns 00h when address locations outside of normal address space are read.
Block reads do not wrap around from address FFh to 00h.
If the master acknowledges more bytes that it requested, the LM96194 continues to supply data until the master does not
acknowledge a byte.
If the master does not acknowledges a byte to prematurely abort a block read, the LM96194 gets off the bus to allow the
master to issue a STOP signal.
2
Slave
Address
11
Read
Command
Code
(F1h)
2
Slave
Address
W
Section 14.5.2 Block Command Code Summary
A
W
3
A
12 13
S
3
A
4
Fixed
Block
Command
Code
(F2h–FDh)
Slave
Address
4
Block
Read
Comman
d
Code
(F1h)
R
A
A
A
5
Byte
Count
(2h)
5
S
6
Slave
Address
14
Byte
Count
(1–20h)
(N)
A
6
Start
Register
Address
R
24
A
for more details on the command codes. Below is the sequence
7
A
15
Data
Byte 1
8
Byte
Count
(N)
A
7
Byte
Count
(1–20h)
(N)
A
A
16
Data
Byte 2
9
Data
Byte 1
A
8
P
A
9
S
A
… Data
10
Slave
Address
10 11
… Data
17
Byte N
Byte N
W
/A
A
12 13
/A
16
P
…
P