LH28F800BJE-PTTL90 Sharp Microelectronics, LH28F800BJE-PTTL90 Datasheet - Page 9

• Manufacturer Part Number: LH28F800BJE-PTTL90
• Description: IC FLASH 8MBIT 90NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F800BJE-PTTL90

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 425-1821; LHF80J01

2 PRINCIPLES OF OPERATION
The product includes an on-chip WSM to manage block
erase, full chip erase, word/byte write and lock-bit
configuration functions. It allows for: fixed power supplies
during block erase, full chip erase, word/byte write and
lock-bit configuration, and minimal processor overhead
with RAM-like interface timings.
After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
voltage on V
erase, word/byte write and lock-bit configurations. All
functions associated with altering memory contents−block
erase,
configuration, status and identifier codes−are accessed via
the CUI and verified through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, full chip erase,
word/byte write and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification and margining of data.
Addresses and data are internally latched during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block
erase, full chip erase, word/byte write and lock-bit
configuration can be stored in any block. This code is
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word/byte write suspend allows system software
to suspend a word/byte write to read data from any other
flash memory array location.
full
CCW
chip
enables successful block erase, full chip
erase,
word/byte
CCW
write,
voltage. High
lock-bit
[A
18
7DFFF
7CFFF
7BFFF
7AFFF
7FFFF
7EFFF
7D000
7A000
77FFF
6FFFF
67FFF
5FFFF
57FFF
4FFFF
47FFF
3FFFF
37FFF
2FFFF
27FFF
1FFFF
17FFF
0FFFF
07FFF
7C000
7B000
79FFF
78FFF
7F000
7E000
70000
68000
60000
58000
50000
48000
40000
38000
30000
28000
20000
18000
10000
08000
00000
79000
78000
-A
0
]
Figure 3. Memory Map
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
4KW/8KB Boot Block
4KW/8KB Boot Block
Top Boot
10
11
12
13
14
1
3
0
1
2
3
4
5
6
7
8
9
0
1
0
2
4
5
[A
FFFFF
FE000
FDFFF
FC000
FBFFF
FA000
F9FFF
F8000
F7FFF
F6000
F5FFF
F4000
F3FFF
F2000
F1FFF
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
18
Rev. 1.27
-A
-1
]