LH28F800BJE-PTTL90 Sharp Microelectronics, LH28F800BJE-PTTL90 Datasheet - Page 18

• Manufacturer Part Number: LH28F800BJE-PTTL90
• Description: IC FLASH 8MBIT 90NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F800BJE-PTTL90

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 425-1821; LHF80J01

4.12 OTP Program Command
OTP program is executed by a two-cycle command
sequence. OTP program command(C0H) is written,
followed by a second write cycle that specifies the address
and data (latched on the rising edge of WE#). The WSM
then takes over, controlling the OTP program and program
verify algorithms internally. After the OTP program
command sequence is completed, the device automatically
outputs status register data when read (see Figure 13). The
CPU can detect the completion of the OTP program by
analyzing the output data of the RY/BY# pin or status
register bit SR.7.
When OTP program is completed, status register bit SR.4
should be checked. If OTP program error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully
program to "0"s. The CUI remains in read status register
mode until it receives other commands.
Reliable OTP program can be executed only when
V
this voltage, memory contents are protected against OTP
CC
=2.7V-3.6V and V
CCW
=V
CCWH1/2
. In the absence of
programs.
V
to "1". If OTP write is attempted when the OTP Lock-bit
is set, SR.1 and SR.4 is set to "1".
4.13 Block Locking by the WP#
This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.
The lockable two boot blocks are locked when WP#=V
any program or erase operation to a locked block will
result in an error, which will be reflected in the status
register. For top configuration, the top two boot blocks are
lockable. For the bottom configuration, the bottom two
boot blocks are lockable. If WP# is V
bit is not set, boot block can be programmed or erased
normally (Unless V
only two boot blocks, other blocks are not affected.
CCW
≤V
CCWLK
If
, status register bits SR.3 and SR.4 is set
OTP
CCW
program
is below V
is
CCWLK
IH
attempted
and block lock-
). WP# is valid
Rev. 1.27
while
IL
;