LH28F800BJE-PTTL90 Sharp Microelectronics, LH28F800BJE-PTTL90 Datasheet - Page 6

• Manufacturer Part Number: LH28F800BJE-PTTL90
• Description: IC FLASH 8MBIT 90NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F800BJE-PTTL90

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 425-1821; LHF80J01

The access time is 90ns (t
temperature range (0°C to +70°C) and V
range of 2.7V-3.6V.
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical I
current is 2µA (CMOS) at 3.0V V
When CE# and RP# pins are at V
standby mode is enabled. When the RP# pin is at GND,
reset
consumption and provides write protection. A reset time
(t
are valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are recognized.
With RP# at GND, the WSM is reset and the status
register is cleared.
Please do not execute reprogramming "0" for the bit which
has already been programed "0". Overwrite operation may
generate unerasable bit. In case of reprogramming "0" to
the data which has been programed "1".
For example, changing data from "10111101" to
"10111100" requires "11111110" programming.
PHQV
·Program "0" for the bit in which you want to change
·Program "1" for the bit which has already been
data from "1" to "0".
programmed "0".
) is required from RP# switching high until outputs
mode
is
enabled
AVQV
which
CC
) over the operating
.
CC
minimizes
, the I
CC
supply voltage
CC
CMOS
power
PHEL
CCR
)
1.3 Product Description
1.3.1 Package Pinout
The product is available in 48-lead TSOP package (see
Figure 2).
1.3.2 Block Organization
This
architecture providing system memory integration. Each
erase block can be erased independently of the others up to
100,000 times. For the address locations of the blocks, see
the memory map in Figure 3.
Boot Blocks: The boot block is intended to replace a
dedicated
microcontroller-based system. This boot block 4K words
(4,096words)
protection to protect the crucial microprocessor boot code
from accidental modification. The protection of the boot
block is controlled using a combination of the V
WP# pins and block lock-bit.
Parameter Blocks: The boot block architecture includes
parameter blocks to facilitate storage of frequently update
small parameters that would normally require an
EEPROM. By using software techniques, the word-rewrite
functionality of EEPROMs can be emulated. Each boot
block component contains six parameter blocks of 4K
words (4,096 words) each. The protection of the parameter
block is controlled using a combination of the V
and block lock-bit.
Main Blocks: The reminder is divided into main blocks for
data or code storage. Each 8M-bit device contains fifteen
32K words (32,768 words) blocks. The protection of the
main block is controlled using a combination of the
V
CCW
, RP# and block lock-bit.
product
boot
features
features
PROM
hardware
an
in
a
asymmetrically-blocked
controllable
microprocessor
CCW
CCW
Rev. 1.27
, RP#,
write-
, RP#
or