LH28F800BJE-PTTL90 Sharp Microelectronics, LH28F800BJE-PTTL90 Datasheet - Page 30

• Manufacturer Part Number: LH28F800BJE-PTTL90
• Description: IC FLASH 8MBIT 90NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F800BJE-PTTL90

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 425-1821; LHF80J01

5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erase, full chip erase, word/byte write or
lock-bit configuration during power transitions. Upon
power-up, the device is indifferent as to which power
supply (V
resets the CUI to read array mode at power-up.
A system designer must guard against spurious writes for
V
both WE# and CE# must be low for a command write,
driving either to V
step command sequence architecture provides added level
of protection against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled while
RP#=V
5.7 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
CC
voltages above V
IL
regardless of its control inputs state.
CCW
or V
IH
CC
will inhibit writes. The CUI’s two-
) powers-up first. Internal circuitry
LKO
when V
CCW
is active. Since
5.8 Data Protection Method
Noises having a level exceeding the limit specified in the
specification may be generated under specific operating
conditions on some systems. Such noises, when induced
onto WE# signal or power supply, may be interpreted as
false commands, causing undesired memory updating. To
protect the data stored in the flash memory against
unwanted overwriting, systems operating with the flash
memory should have the following write protect designs,
as appropriate:
1) Protecting data in specific block
When a lock bit is set, the corresponding block (includes
the 2 boot blocks) is protected against overwriting. By
setting a WP# to low, only the 2 boot blocks can be
protected against overwriting. By using this feature, the
flash memory space can be divided into the program
section (locked section) and data section (unlocked
section). The permanent lock bit can be used to prevent
false block bit setting. For further information on
setting/resetting lock-bit, refer to the specification. (See
chapter 4.10 and 4.11.)
2) Data protection through V
When the level of V
voltage), write operation on the flash memory is disabled.
All blocks are locked and the data in the blocks are
completely write protected. For the lockout voltage, refer
to the specification. (See chapter 6.2.3.)
3) Data protection through RP#
When the RP# is kept low during read mode, the flash
memory will be reset mode, then write protecting all
blocks. When the RP# is kept low during power up and
power down sequence such as voltage transition, write
operation on the flash memory is disabled, write
protecting all blocks. For the details of RP# control, refer
to the specification. (See chapter 5.6 and 6.2.7.)
CCW
is lower than V
CCW
CCWLK
Rev. 1.27
(lockout