LH52256C-70LL Sharp Microelectronics, LH52256C-70LL Datasheet

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LH52256C-70LL

Manufacturer Part Number
LH52256C-70LL
Description
IC SRAM 256KBIT 70NS 28DIP
Manufacturer
Sharp Microelectronics
Datasheet

Specifications of LH52256C-70LL

Rohs Status
RoHS non-compliant
Format - Memory
RAM
Memory Type
SRAM
Memory Size
256K (32K x 8)
Speed
70ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Other names
425-1833-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LH52256C-70LL
Manufacturer:
SHARP
Quantity:
3 198
Part Number:
LH52256C-70LL
Manufacturer:
SHARP
Quantity:
4 600
LH52256C/CH
FEATURES
DESCRIPTION
32,768
mode. It is fabricated using silicon-gate CMOS process
technology.
The LH52256C is a Static RAM organized as
32,768
Access time: 70 ns (MAX.)
Supply current:
Data retention current: 1.0 A (MAX.)
Wide operating voltage range:
Operating temperature:
Fully-static operation
Three-state outputs
Not designed or rated as radiation
hardened
Package:
N-type bulk silicon
Operating: 45 mA (MAX.)
Standby: 40 A (MAX.)
Commerical temperature 0 C to +70 C
Industrial temperature -40° to +85°C
28-pin, 600-mil DIP
28-pin, 450-mil SOP
28-pin, 300-mil SK-DIP
28-pin, 8
10 mA (MAX.) (t
(V
4.5 V
8 bits which provides low-power standby
CCDR
8 bit organization
= 3 V, T
5.5 V
3 mm
2
A
RC
TSOP (Type I)
= 25 C)
, t
WC
= 1 s)
PIN CONNECTIONS
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
28-PIN TSOP (Type I)
NOTE: Reverse bend available on request.
V
WE
A
A
A
OE
A
A
A
CC
A
A
A
A
A
Figure 2. TSOP (Type I) Pin Connections
13
14
12
11
8
7
5
4
3
9
6
CMOS 256K (32K
10
12
13
14
11
2
3
4
5
6
7
8
9
1
Figure 1. Pin Connections
GND
I/O
I/O
I/O
A
A
A
A
A
A
A
A
A
A
14
12
7
6
4
2
3
5
3
0
2
1
1
10
12
13
14
11
2
3
4
5
6
7
8
9
1
28
26
19
18
17
16
15
27
25
24
23
22
20
21
8) Static RAM
A
CE
I/O
I/O
I/O
I/O
I/O
V
WE
A
A
A
OE
A
CC
13
11
10
8
9
7
5
4
8
6
16
28
27
26
25
24
23
22
20
19
18
17
15
21
TOP VIEW
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
52256C-1
52256C-8
10
0
1
2
8
3
2
1
7
6
5
4
1

Related parts for LH52256C-70LL

LH52256C-70LL Summary of contents

Page 1

... SOP 28-pin, 300-mil SK-DIP 2 28-pin TSOP (Type I) N-type bulk silicon DESCRIPTION The LH52256C is a Static RAM organized as 32,768 8 bits which provides low-power standby mode fabricated using silicon-gate CMOS process technology. CMOS 256K (32K PIN CONNECTIONS 28-PIN DIP 28-PIN SK-DIP ...

Page 2

... Address inputs 0 14 Chip enable CE Write enable WE OE Output enable 2 MEMORY ARRAY (512 x 512) 8 COLUMN I/O CIRCUIT OUTPUT BUFFERS 8 COLUMN DECODER INPUT DATA CONTROL Figure 3. LH52256C Block Diagram SIGNAL I GND CMOS 256K (32K 8) Static RAM GND I/O ...

Page 3

... Undershoot of -3 allowed width of pulse below 50 ns. I/O - I/O SUPPLY CURRENT 1 8 High impedance Standby (I Data output Active (I High impedance Active (I Data input Active (I RATING UNIT –0.5 to +7.0 V –0 0 +70 C –65 to +150 + MIN. TYP. MAX. UNIT 4.5 5.0 5.5 2 0.5 CC –0.5 0.8 LH52256C/CH NOTE ) NOTE NOTE ...

Page 4

... LH52256C/CH DC ELECTRICAL CHARACTERISTICS (T PARAMETER SYMBOL Input leakage I LI current Output leakage I LO current Minimum cycle Operating supply current CC1 I SB Standby current I SB1 V OL Output voltage V OH NOTE: Typical values 5 ELECTRICAL CHARACTERISTICS AC Test Conditions PARAMETER Input pulse level Input rise and fall time Input and output timing Ref ...

Page 5

... Chip enable hold time NOTE Read cycle time Typical values 4 5 MIN. MAX. UNIT OHZ MIN. TYP. MAX I + CONDITIONS CE V – 0.2 V CCDR CCDR CCDR – 0.2 V CCDR CDR t R LH52256C/CH NOTE UNIT NOTE MIN. TYP. MAX. UNIT NOTE 2.0 5.5 V 0.3 1 ...

Page 6

... LH52256C/CH ADDRESS OUT NOTE HIGH for Read Cycle. 6 CMOS 256K (32K ACE OLZ DATA VALID Figure 4. Read Cycle 8) Static RAM OHZ t OH 52256C-3 ...

Page 7

... LOW, the outputs remain in high impedance state goes HIGH simulaneously with WE going HIGH or before WE going HIGH, the outputs remain in high impedance state (NOTE (NOTE 3) (NOTE 1) t OHZ (NOTE 5) is measured from the beginning Figure 5. Write Cycle (OE Controlled) LH52256C/CH t (NOTE (NOTE DATA VALID 52256C-4 7 ...

Page 8

... LH52256C/CH ADDRESS OUT D IN NOTES write occurs during the overlap of a LOW CE, and a LOW WE. A write begins at the latest transition among CE going LOW, and WE going LOW. A write ends at the earliest transition among CE going HIGH, and WE going HIGH write to the end of write. ...

Page 9

... LH52256C/CH DETAIL 0.30 [0.012] 0.20 [0.008] 15.24 [0.600] TYP. 28DIP-2 10.60 [0.417] 0.20 [0.008] 0.10 [0.004] 28SOP 9 ...

Page 10

... LH52256C/CH 28SDIP (SDIP28-P-400 25.75 [1.014] 25.25 [0.994] 1.78 [0.070] TYP. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 28TSOP (TSOP028-P-0813) 0.28 [0.011] 0.55 [0.022] 0.12 [0.005] TYP 8.20 [0.323] 7.80 [0.307] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ...

Page 11

... Static RAM ORDERING INFORMATION LH52256C X X Device Type Operating Package Temp Example: LH52256C-70LL (CMOS 32K x 8 Static RAM, Low-Low-power standby, 70 ns, 28-pin, 600-mil DIP Speed Power Low-Low-power standby 70 Access Time (ns) Blank 28-pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil SK-DIP (DIP028-P-0300) N 28-pin, 450-mil SOP (SOP028-P-0450) ...

Page 12

... SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Fax: (360) 834-8903 http://www.sharpsma.com EUROPE SHARP Microelectronics Europe Sonninstraße 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Fax: (49) 40 2376-2232 http://www.sharpsme.com ASIA SHARP Corporation Integrated Circuits Group ...

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