LH28F800BJE-PTTL90 Sharp Microelectronics, LH28F800BJE-PTTL90 Datasheet

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LH28F800BJE-PTTL90

Manufacturer Part Number
LH28F800BJE-PTTL90
Description
IC FLASH 8MBIT 90NS 48TSOP
Manufacturer
Sharp Microelectronics
Datasheet

Specifications of LH28F800BJE-PTTL90

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8 or 512K x 16)
Speed
90ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
425-1821
LHF80J01

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P
S
RODUCT
PECIFICATIONS
Integrated Circuits Group
®
LH28F800BJE-PTTL90
Flash Memory
8M (512K × 16/1M × 8)
(Model No.: LHF80J01)
Spec No.: EL132002
Issue Date: February 1, 2001

Related parts for LH28F800BJE-PTTL90

LH28F800BJE-PTTL90 Summary of contents

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... P S RODUCT PECIFICATIONS LH28F800BJE-PTTL90 Flash Memory 8M (512K × 16/1M × 8) Issue Date: February 1, 2001 ® (Model No.: LHF80J01) Spec No.: EL132002 Integrated Circuits Group ...

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Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please observe ...

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INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 1.3 Product Description...................................................... 4 1.3.1 Package Pinout ....................................................... 4 1.3.2 Block Organization................................................. 4 2 PRINCIPLES OF OPERATION........................................ 7 2.1 Data Protection............................................................. 8 3 BUS OPERATION ............................................................ 8 3.1 Read.............................................................................. ...

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... These alternatives give designers ultimate control of their code security needs. The product is manufactured on SHARP’s 0.25µm ETOX 48-lead TSOP, ideal for board constrained applications. *ETOX is a trademark of Intel Corporation. LH28F800BJE-PTTL90 ■ Enhanced Automated Suspend Options Word/Byte Write Suspend to Read Block Erase Suspend to Word/Byte Write Block Erase Suspend to Read ■ ...

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... INTRODUCTION This datasheet contains the product specifications. Section 1 provides a flash memory overview. Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Features Key enhancements of the product are: •Single low voltage operation •Low power consumption •Enhanced Suspend Capabilities • ...

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... Each minimizes power erase block can be erased independently of the others up to 100,000 times. For the address locations of the blocks, see the memory map in Figure 3. ) PHEL Boot Blocks: The boot block is intended to replace a dedicated microcontroller-based system. This boot block 4K words ...

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Output Buffer Y Input A -A Decoder -1 18 Buffer Address X Decoder Latch Address Counter Figure 1. Block Diagram ...

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... Boot and Parameter Block Address DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register and identifier code read cycles. Data pins float to high- INPUT/ DQ -DQ impedance when the chip is deselected or outputs are disabled. Data is internally latched during a ...

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... RAM-like interface timings. After initial device power-up or return from reset mode (see section 3 Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby and output disable operations. Status register and identifier codes can be accessed ...

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... Refer to Table 5 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes ...

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... Device Code 00001 Manufacturer Code Main Block 14 00000 Figure 4. Device Identifier Code Memory Map 3.6 OTP(One Time Program) Block outputs the The OTP block is a special block that can not be erased. The block is divided into two parts. One is a factory program area where a unique number can be written according to customer requirements in SHARP factory ...

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... OE# WE ≤V , memory contents can be read, but not altered. CCW CCWLK or V CCWLK CCWH1/2 voltage ≤V , read operations from CCW CCWLK on V enables successful block CCWH1/2 CCW (1, Address V DQ RY/BY# CCW 0- OUT X X High High High Z High Z See X Note 5 High Z Figure ...

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... X=Any valid address within the device. IA=Identifier Code Address: see Figure 4. BA=Address within the block being erased or locked. WA=Address of memory location to be written. OA=Address of OTP block to be written: see Figure 5. 3. ID=Data read from identifier codes. SRD=Data read from status register. See Table 6 for a description of the status register bits. ...

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... Future Use Permanent Lock Configuration 00003H •Device is Unlocked •Device is Locked •Reserved for Future Use NOTE selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map don’t care in byte mode -DQ outputs 00H in word mode ...

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... The CUI remains in read status register mode until it receives another command. Reliable V =2.7V-3.6V and V CC this high voltage, memory contents are protected against word/byte writes. If word/byte write is attempted while ≤V V CCW CCWLK set to "1". Successful word/byte write requires for boot blocks that WP bit be cleared ...

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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to V ...

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Set Block and Permanent Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a permanent lock-bit and WP# pin. The block lock-bits and WP# pin gates program and erase operations while ...

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... If OTP write is attempted when the OTP Lock-bit is set, SR.1 and SR.4 is set to "1". 4.13 Block Locking by the WP# This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary ...

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Permanent Operation V RP# CCW Lock-Bit Block Erase ≤V X CCWLK or >V V CCWLK IL Word/Byte V IH Write ≤V Full Chip X CCWLK Erase >V V CCWLK ≤V Set Block X CCWLK Lock-Bit >V V ...

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WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE ...

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Start Write 70H Read Status Register 0 SR.7= 1 Write 20H Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status ...

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Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above Range ...

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Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H Write Word/Byte Data and Address Read Status Register Suspend Word/Byte No Suspend 0 SR.7= Word/Byte Yes Write 1 Full Status Check if Desired Word/Byte Write Complete FULL ...

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Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Read or Word/Byte Write Read Word/Byte Write ? Read Array Data Word/Byte Write Loop No Done? Yes Write D0H Write FFH Read Array Data Block ...

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Start Write B0H Read Status Register 0 SR. Word/Byte Write Completed SR.2= 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Word/Byte Write Resumed Read Array Data Figure 10. Word/Byte Write Suspend/Resume Flowchart ...

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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write 01H/F1H, Block/Device Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= ...

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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above Range ...

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Start Write 70H Read Status Register 0 SR.7= 1 Write C0H Write Data and Address Read Status Register 0 SR.7= 1 Full Status Check if Desired OTP Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= ...

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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. ...

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... By setting a WP# to low, only the 2 boot blocks can be protected against overwriting. By using this feature, the flash memory space can be divided into the program section (locked section) and data section (unlocked section). The permanent lock bit can be used to prevent false block bit setting ...

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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration ................0°C to +70°C Storage Temperature During under Bias ............................... -10°C to +80°C During non Bias ................................ -65°C to +125°C ...

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AC Input/Output Test Conditions 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% ...

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DC Characteristics Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Auto Power-Save Current CCAS Reset Power-Down Current CCD Read Current CCR ...

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Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout during Normal CCWLK CCW Operations V V during ...

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AC Characteristics - Read-Only Operations Sym. t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# to ...

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Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV V ...

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Standby Address Selection V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z DATA(D/Q) ...

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AC Characteristics - Write Operations Sym. t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP#V Setup to WE# Going ...

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V IH ADDRESSES( CE#( ELWL V IH OE#( WE#( High Z DATA(D/ BYTE#( High Z ("1") RY/BY#(R) (SR.7) V ...

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Alternative CE#-Controlled Writes Sym. t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP#V Setup to CE# Going High SHEH ...

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V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ BYTE#( High Z ("1") RY/BY#(R) (SR. ...

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Reset Operations High Z ("1") RY/BY#(R) (SR. ("0" RP#( High Z ("1") RY/BY#(R) (SR. ("0" RP#( (B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit ...

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Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Performance Sym. Parameter t Word Write Time WHQV1 t EHQV1 Byte Write Time Block Write Time (In word mode) Block Write Time (In byte mode) t WHQV2 Block Erase ...

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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...

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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...

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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...

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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...

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... SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Fax: (360) 834-8903 http://www.sharpsma.com EUROPE SHARP Microelectronics Europe Sonninstraße 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Fax: (49) 40 2376-2232 http://www.sharpsme.com ASIA SHARP Corporation Integrated Circuits Group ...

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