LH28F800BJE-PTTL90 Sharp Microelectronics, LH28F800BJE-PTTL90 Datasheet - Page 13

• Manufacturer Part Number: LH28F800BJE-PTTL90
• Description: IC FLASH 8MBIT 90NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F800BJE-PTTL90

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 425-1821; LHF80J01

NOTES:
1. BUS operations are defined in Table 2.1 and Table 2.2.
2. X=Any valid address within the device.
3. ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock configuration and
5. If WP# is V
6. Either 40H or 10H are recognized by the WSM as the word/byte write setup.
7. The clear block lock-bits operation simultaneously clears all block lock-bits.
8. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done.
9. Once the permanent lock-bit is set, permanent lock-bit reset is unable.
10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
Word/Byte Write
Block Erase and Word/Byte
Write Suspend
Block Erase and Word/Byte
Write Resume
Set Block Lock-Bit
Clear Block Lock-Bits
Set Permanent Lock-Bit
OTP Program
IA=Identifier Code Address: see Figure 4.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
OA=Address of OTP block to be written: see Figure 5.
SRD=Data read from status register. See Table 6 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
OD=Data to be written at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
permanent lock configuration codes. See Section 4.2 for read identifier code data.
bits. The parameter and main blocks are locked by block lock-bits without WP# state.
used.
Command
IL
, boot blocks are locked without block lock-bits state. If WP# is V
Bus Cycles
Req’d.
≥2
1
2
1
2
2
2
1
1
2
2
2
2
Table 3. Command Definitions
Notes
5,6
7,8
4
5
5
5
8
9
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
(1)
First Bus Cycle
Addr
X
X
X
X
X
X
X
X
X
X
X
X
X
(2)
(10)
Data
40H or
D0H
IH
FFH
B0H
C0H
90H
70H
50H
20H
30H
10H
60H
60H
60H
, boot blocks are locked by block lock-
(3)
Oper
Write
Write
Write
Write
Write
Write
Write
Read
Read
(1)
Second Bus Cycle
Addr
WA
BA
BA
OA
IA
X
X
X
X
(2)
Rev. 1.27
Data
SRD
D0H
D0H
D0H
WD
01H
F1H
OD
ID
(3)