LH28F800 Sharp Electrionic Components, LH28F800 Datasheet
LH28F800
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LH28F800 Summary of contents
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... TSOP, CSP) DESCRIPTION The LH28F800SG-L/SGH-L flash memories with SmartVoltage technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. The LH28F800SG-L/SGH-L can operate 2.7 V and V CC low voltage operation capability realizes longer battery life and suits for cellular phone application. ...
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... COMPARISON TABLE VERSIONS OPERATING TEMPERATURE LH28F800SG +70˚C (FOR TSOP, CSP) LH28F800SGH-L – +85˚C (FOR TSOP, CSP) 1 LH28F800SG +70˚C (FOR SOP) 1 Refer to the datasheet of LH28F800SG-L (FOR SOP). PIN CONNECTIONS 48-PIN TSOP (Type ...
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... BLOCK DIAGRAM Y DECODER INPUT BUFFER ADDRESS LATCH X DECODER ADDRESS COUNTER LH28F800SG-L/SGH-L (FOR TSOP, CSP OUTPUT INPUT BUFFER BUFFER IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR Y GATING 16 32 k-WORD BLOCKS - LOGIC CE# WE# COMMAND OE# USER INTERFACE WP# RP# RY/BY# WRITE ...
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... GND SUPPLY GROUND : Do not float any ground pins CONNECT : Lead is not internal connected; recommend to be floated. LH28F800SG-L/SGH-L (FOR TSOP, CSP) NAME AND FUNCTION allows to set permanent lock-bit. Block erase, word write, or lock-bit HH < RP# < V produce spurious results and should not be ...
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... V combinations, as shown in Table meet system performance and power expectations. 2 consumes approximately one-fifth CC LH28F800SG-L/SGH-L (FOR TSOP, CSP) the power But highest read performance eliminates the need for a separate 12 V converter, while maximizes block erase PP and word write performance ...
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... The access time the V AVQV voltage range of 4.75 to 5.25 V over the temperature range +70°C (LH28F800SG-L)/ – +85°C (LH28F800SGH-L). At 4 the access time 100 ns. At lower CC V voltage, the access time 100 ...
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... Read Array command. Block erase suspend allows system software to suspend a block erase to read/write LH28F800SG-L/SGH-L (FOR TSOP, CSP) data from/to blocks other than that which is suspended. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location ...
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... After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. LH28F800SG-L/SGH-L (FOR TSOP, CSP) During block erase, word write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid ...
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... Device Code 00001 Manufacture Code 00000 Fig. 2 Device Identifier Code Memory Map LH28F800SG-L/SGH-L (FOR TSOP, CSP) 3.6 Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. The Block Erase command requires appropriate command data and an address within the block to be erased ...
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... OL block erase, word write, or lock-bit configuration algorithms during when the WSM is not busy block erase suspend mode (with word write inactive), word write suspend mode, or deep power-down mode. LH28F800SG-L/SGH-L (FOR TSOP, CSP) Table 2 Bus Operations RP# CE# OE# WE ...
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... RP# must enable block erase or word write operations. Attempts to issue a block erase or word write to a locked block while WP RP LH28F800SG-L/SGH-L (FOR TSOP, CSP) Table 3 Command Definitions FIRST BUS CYCLE NOTE (NOTE 1) (NOTE 2) ’ D. Oper Addr ...
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... LH28F800SG-L/SGH-L (FOR TSOP, CSP) 4.3 Read Status Register Command The status register may be read to determine when a block erase, word write, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command ...
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... After the word write sequence is written, the device automatically outputs status register data when read (see Fig. 4). The CPU can detect the LH28F800SG-L/SGH-L (FOR TSOP, CSP) completion of the word write event by analyzing the RY/BY# pin or status register bit SR.7. When word write is complete, status register bit SR ...
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... Word Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word write operation has been suspended (both will be set to "1"). RY/BY# will LH28F800SG-L/SGH-L (FOR TSOP, CSP) also transition to V the word write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended ...
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... Set permanent lock-bit operations with V < RP# < V produce spurious results and should HH not be attempted. LH28F800SG-L/SGH-L (FOR TSOP, CSP) 4.10 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the permanent lock-bit not set and WP ...
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... Lock-Bit 1 Set Permanent X X Lock-Bit 0 Clear Block X Lock-Bits 1 LH28F800SG-L/SGH-L (FOR TSOP, CSP) lock-bits is required to initialize block lock-bit contents to known values. Once the permanent lock-bit is set, it cannot be cleared. Table 5 Write Protection Alternatives WP# RP Block Erase and Word Write Enabled ...
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... Word Write Suspended 0 = Word Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS Permanent Lock-Bit, Block Lock-Bit and/or WP#/RP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) LH28F800SG-L/SGH-L (FOR TSOP, CSP) Table 6 Status Register Definition WWSLBS VPPS 4 3 NOTES : Check RY/BY# or SR.7 to determine block erase, word write, or lock-bit configuration completion ...
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... Command Sequence SR. Error 0 1 Block Erase SR.5 = Error 0 Block Erase Successful Fig. 3 Automated Block Erase Flowchart LH28F800SG-L/SGH-L (FOR TSOP, CSP) BUS COMMAND COMMENTS OPERATION Data = 20H Write Erase Setup Addr = Within Block to be Erased Erase Data = D0H Write Confirm Addr = Within Block to be Erased ...
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... SR.1 = Device Protect Error 0 1 SR.4 = Word Write Error 0 Word Write Successful Fig. 4 Automated Word Write Flowchart LH28F800SG-L/SGH-L (FOR TSOP, CSP) BUS COMMAND COMMENTS OPERATION Setup Data = 40H Write Word Write Addr = Location to be Written Data = Data to be Written Write Word Write ...
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... Word Write? Read Array Data Word Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed Array Data Fig. 5 Block Erase Suspend/Resume Flowchart LH28F800SG-L/SGH-L (FOR TSOP, CSP) BUS COMMAND OPERATION Erase Write Suspend Read Standby Standby Erase Write Resume ...
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... Read Array Data No Done Reading Yes Write D0H Write FFH Read Word Write Resumed Array Data Fig. 6 Word Write Suspend/Resume Flowchart LH28F800SG-L/SGH-L (FOR TSOP, CSP) BUS COMMAND COMMENTS OPERATION Word Write Data = B0H Write Suspend Addr = X Status Register Data Read Addr = X Check SR ...
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... Command Sequence SR. Error 0 1 Set Lock-Bit SR.4 = Error 0 Set Lock-Bit Successful Fig. 7 Set Block and Permanent Lock-Bit Flowchart LH28F800SG-L/SGH-L (FOR TSOP, CSP) BUS COMMAND COMMENTS OPERATION Set Data = 60H Block/Permanent Write Addr = Block Address (Block), Lock-Bit Device Address (Parmanent) Setup Set ...
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... Command Sequence SR. Error 0 1 Clear Block Lock-Bits SR.5 = Error 0 Clear Block Lock-Bits Successful Fig. 8 Clear Block Lock-Bits Flowchart LH28F800SG-L/SGH-L (FOR TSOP, CSP) BUS COMMAND COMMENTS OPERATION Clear Block Data = 60H Write Lock-Bits Addr = X Setup Clear Block Data = D0H Write Lock-Bits ...
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... LH28F800SG-L/SGH-L (FOR TSOP, CSP) issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks ...
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... In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP regardless of its control inputs IL state. LH28F800SG-L/SGH-L (FOR TSOP, CSP) 5.7 Power Consumption clear the status IL When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’ ...
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... Supply Voltage (5.0±0.5 V) CC4 CC NOTE : 1. Test condition : Ambient temperature LH28F800SG-L/SGH-L (FOR TSOP, CSP) NOTICE : The specifications are subject to change without notice. Verify with your local SHARP sales office that you have the latest datasheet before finalizing a design. WARNING : Stressing the device beyond the ...
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... V. Input rise and fall times (10% to 90%) < 10 ns. Fig. 10 Transient Input/Output Reference Waveform for V 2.4 INPUT 0.45 AC test inputs are driven at V begins and V IH TTL 90%) < 10 ns. Fig. 11 Transient Input/Output Reference Waveform for LH28F800SG-L/SGH-L (FOR TSOP, CSP + MHz ˚ A TYP. MAX 1.35 TEST POINTS 1 ...
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... Includes Jig L Capacitance Fig. 12 Transient Equivalent Testing Load Circuit LH28F800SG-L/SGH-L (FOR TSOP, CSP) Test Configuration Capacitance Loading Value TEST CONFIGURATION V = 3.3±0.3 V, 2 (NOTE 5.0±0. 5.0±0 NOTE : 1. Applied to high-speed products, LH28F800SG-L70 and LH28F800SGH-L70. OUT - (pF 100 ...
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... PP I PPW Set Lock-Bit Current V Block Erase Clear Block Lock-Bits PPE Current I V Word Write or Block PPWS PP I Erase Suspend Current PPES LH28F800SG-L/SGH-L (FOR TSOP, CSP 2 5.0±0 NOTE TYP. MAX. TYP. 1 ±0.5 1 ±0.5 100 ...
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... V inhibited when V , and not guaranteed in the PP PPLK range between V (max.) and V PPLK V (max.) and V (min.), between V PPH1 PPH2 and V (min.), and above V PPH3 PPH3 LH28F800SG-L/SGH-L (FOR TSOP, CSP 2 5.0±0 NOTE MIN. MAX. MIN. 7 –0.5 0.8 –0 ...
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... OE# Change, Whichever Occurs First NOTES : 1. See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate. 2. OE# may be delayed ELQV GLQV 3. Sampled, not 100% tested. LH28F800SG-L/SGH-L (FOR TSOP, CSP –40 to +85 C ˚ ˚ LH28F800SG-L70 LH28F800SGH-L70 NOTE MIN ...
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... CE# without impact on t ELQV 3. Sampled, not 100% tested. 4. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. LH28F800SG-L/SGH-L (FOR TSOP, CSP +70˚C or –40 to +85 C ˚ (NOTE 4) LH28F800SG-L70 V ± ...
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... WE# ( High Z DATA (D/Q) ( RP# ( Fig Waveform for Read Operations LH28F800SG-L/SGH-L (FOR TSOP, CSP) Device Data Valid Address Selection Address Stable t AVAV t ELQV t GLQV t GLQX t ELQX Valid Output t AVQV t PHQV - EHQZ ...
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... NOTES : 1. Read timing characteristics during block erase, word write and lock-bit configuration operations are the same as during read-only operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations. 2. Sampled, not 100% tested. LH28F800SG-L/SGH-L (FOR TSOP, CSP –40 to +85 C ˚ ˚ LH28F800SG-L70 ...
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... D IN word write, or lock-bit configuration should be held at V (and if necessary RP# PP PPH1/2/3 should be held until determination of block erase, HH word write, or lock-bit configuration success (SR.1/3/4/5 = 0). LH28F800SG-L/SGH-L (FOR TSOP, CSP +70˚C or –40 to +85 C ˚ (NOTE 5) LH28F800SG-L70 V ±0. LH28F800SGH-L70 V ±0.5 V ...
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... Write block erase or word write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. Fig Waveform for WE#-Controlled Write Operations LH28F800SG-L/SGH-L (FOR TSOP, CSP) (NOTE 3) (NOTE 4) (NOTE ...
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... QVPH HH NOTES : 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. LH28F800SG-L/SGH-L (FOR TSOP, CSP) C ˚ LH28F800SG-L70 LH28F800SGH-L70 NOTE MIN. MAX. 100 ...
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... D IN word write, or lock-bit configuration should be held at V (and if necessary RP# PP PPH1/2/3 should be held until determination of block erase, HH word write, or lock-bit configuration success (SR.1/3/4/5 = 0). LH28F800SG-L/SGH-L (FOR TSOP, CSP +70˚C or –40 to +85 C ˚ (NOTE 5) LH28F800SG-L70 V ±0. LH28F800SGH-L70 V ±0.5 V ...
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... Write block erase or word write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. Fig Waveform for CE#-Controlled Write Operations LH28F800SG-L/SGH-L (FOR TSOP, CSP) (NOTE 3) (NOTE 4) (NOTE ...
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... These specifications are valid for all product versions (packages and speeds RP# is asserted while a block erase, word write, or lock-bit configuration operation is not executing, the reset will complete within 100 ns. LH28F800SG-L/SGH-L (FOR TSOP, CSP) t PLPH (A) Reset During Read Array Mode t ...
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... WHRH2 t Time to Read EHRH2 NOTES : 1. Typical values measured +25˚C and nominal A voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. LH28F800SG-L/SGH-L (FOR TSOP, CSP) ˚ 2 (NOTE 1) MIN. TYP. MAX. MIN. TYP. ...
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... Erase Suspend Latency Time to Read t EHRH2 NOTES : 1. Typical values measured +25˚C and nominal A voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. LH28F800SG-L/SGH-L (FOR TSOP, CSP +70˚C or –40 to +85 ˚ NOTE MIN. TYP ...
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... V CC OPTION ORDER CODE 1.35 V I/O Levels 1 LH28F800SGXX-L70 2 LH28F800SGXX-L10 LH28F800SG-L/SGH-L (FOR TSOP, CSP) Access Speed (ns (5.0 0.25 V (5.0 0.5 V (3.3 0.3 V), 100 ns (2 100 ns (5.0 0.5 V), 100 ns (3.3 0.3 V), 120 ns (2.7 to 3.0 V) Package E = 48-pin TSOP (I) (TSOP048-P-1220) Normal bend R = 48-pin TSOP (I) (TSOP048-P-1220) Reverse bend ...
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TSOP (TSOP048-P-1220 20.0 0.3 18.4 0.2 Package base plane 0.1 19.0 PACKAGING ...
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CSP (FBGA048-P-0808) 0.1 S 0.8 0 0.1 S TYP. 0 0.2 8 TYP. TYP 1.2 0.03 0. PACKAGING Land hole ...