LH28F800BJE-PTTL90 Sharp Microelectronics, LH28F800BJE-PTTL90 Datasheet - Page 15

• Manufacturer Part Number: LH28F800BJE-PTTL90
• Description: IC FLASH 8MBIT 90NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F800BJE-PTTL90

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 425-1821; LHF80J01

4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH/FFH). Block preconditioning, erase, and verify
are handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence is
written, the device automatically outputs status register
data when read (see Figure 6). The CPU can detect block
erase completion by analyzing the output data of the
RY/BY# pin or status register bit SR.7.
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to "1". Also, reliable block erasure can only occur when
V
this high voltage, block contents are protected against
erasure. If block erase is attempted while V
SR.3 and SR.5 will be set to "1". Successful block erase
requires for boot blocks that WP# is V
corresponding block lock-bit be cleared. In parameter and
main blocks case, it must be cleared the corresponding
block lock-bit. If block erase is attempted when the
excepting above conditions, SR.1 and SR.5 will be set to
"1".
4.6 Full Chip Erase Command
This command followed by a confirm command erases all
of the unlocked blocks. A full chip erase setup (30H) is
first written, followed by a full chip erase confirm (D0H).
After a confirm command is written, device erases the all
unlocked blocks block by block. This command sequence
requires appropriate sequencing. Block preconditioning,
erase and verify are handled internally by the WSM
(invisible to the system). After the two-cycle full chip
erase sequence is written, the device automatically outputs
status register data when read (see Figure 7). The CPU can
detect full chip erase completion by analyzing the output
data of the RY/BY# pin or status register bit SR.7.
When the full chip erase is complete, status register bit
SR.5 should be checked. If erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
CC
=2.7V-3.6V and V
CCW
=V
CCWH1/2
. In the absence of
CCW
IH
≤V
and the
CCWLK
,
status register mode until a new command is issued. If
error is detected on a block during full chip erase
operation, WSM stops erasing. Full chip erase operation
start from lower address block, finish the higher address
block. Full chip erase can not be suspended.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Full Chip Erase command sequence
will result in both status register bits SR.4 and SR.5 being
set to "1". Also, reliable full chip erasure can only occur
when V
absence of this high voltage, block contents are protected
against erasure. If full chip erase is attempted while
V
Successful full chip erase requires for boot blocks that
WP# is V
cleared. In parameter and main blocks case, it must be
cleared the corresponding block lock-bit. If all blocks are
locked, SR.1 and SR.5 will be set to "1".
4.7 Word/Byte Write Command
Word/Byte write is executed by a two-cycle command
sequence. Word/Byte write setup (standard 40H or
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 8). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
Reliable
V
this high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
V
set to "1". Successful word/byte write requires for boot
blocks that WP# is V
bit be cleared. In parameter and main blocks case, it must
be cleared the corresponding block lock-bit. If word/byte
write is attempted when the excepting above conditions,
SR.1 and SR.4 will be set to "1".
CCW
CC
CCW
=2.7V-3.6V and V
≤V
≤V
CC
CCWLK
CCWLK
word/byte writes can only occur when
IH
=2.7V-3.6V and V
and the corresponding block lock-bit be
, SR.3 and SR.5 will be set to "1".
, status register bits SR.3 and SR.4 will be
IH
CCW
and the corresponding block lock-
=V
CCWH1/2
CCW
=V
. In the absence of
CCWH1/2
. In the
Rev. 1.27