TDGL007 Microchip Technology, TDGL007 Datasheet - Page 87

• Manufacturer Part Number: TDGL007
• Description: Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
• Manufacturer: Microchip Technology

Specifications of TDGL007

• Product: Development Boards
• Interface Type: CAN, I2C
• Operating Supply Voltage: 5 V

7.0
The
dsPIC33FJXXXMCX06A/X08A/X10A family of devices
reduces the numerous peripheral interrupt request
signals to a single interrupt request signal to the
dsPIC33FJXXXMCX06A/X08A/X10A CPU. It has the
following features:
• Up to eight processor exceptions and software
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
• Fixed interrupt entry and return latencies
7.1
The Interrupt Vector Table (IVT) is shown in
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
eight nonmaskable trap vectors plus up to 118 sources
of interrupt. In general, each interrupt source has its
own vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this priority is linked to their position in the
vector table. All other things being equal, lower
addresses have a higher natural priority. For example,
the interrupt associated with vector 0 will take priority
over interrupts at any other vector address.
© 2011 Microchip Technology Inc.
traps
source
support
Note 1: This data sheet summarizes the fea-
2: Some registers and associated bits
INTERRUPT CONTROLLER
Interrupt Vector Table
interrupt
tures of the dsPIC33FJXXXMCX06A/
X08A/X10A family of devices. How-
ever, it is not intended to be a compre-
hensive
complement the information in this data
sheet, refer to Section 6. “Interrupts”
(DS70184) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
reference
dsPIC33FJXXXMCX06A/X08A/X10A
controller
source.
for
Figure
7-1.
the
To
in
The dsPIC33FJXXXMCX06A/X08A/X10A family of
devices implement up to 67 unique interrupts and five
nonmaskable traps. These are summarized in
Table 7-1
7.1.1
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in
AIVT
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a means to
switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
7.2
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The
clears its registers in response to a Reset, which forces
the PC to zero. The digital signal controller then begins
program execution at location 0x000000. The user pro-
grams a GOTO instruction at the Reset address, which
redirects program execution to the appropriate start-up
routine.
Note:
dsPIC33FJXXXMCX06A/X08A/X10A
is
Reset Sequence
and
provided
ALTERNATE INTERRUPT VECTOR
TABLE
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
Table
7-2.
by
the
Figure
ALTIVT
7-1. Access to the
DS70594C-page 87
control
device
bit