TDGL007 Microchip Technology, TDGL007 Datasheet - Page 84
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TDGL007
Manufacturer Part Number
TDGL007
Description
Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
Manufacturer
Microchip Technology
Datasheet
1.TDGL007.pdf
(362 pages)
Specifications of TDGL007
Product
Development Boards
Interface Type
CAN, I2C
Operating Supply Voltage
5 V
- Current page: 84 of 362
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TABLE 6-1:
6.1
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to
further details.
TABLE 6-2:
DS70594C-page 84
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
Note: All Reset flag bits may be set or cleared by the user software.
Reset Type
WDTR
MCLR
SWR
POR
BOR
Clock Source Selection at Reset
Section 9.0 “Oscillator Configuration”
Flag Bit
Oscillator Configuration bits
(FNOSC<2:0>)
COSC Control bits
(OSCCON<14:12>)
RESET FLAG BIT OPERATION
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
Table
Trap conflict event
Illegal opcode or uninitialized
W register access
MCLR Reset
RESET instruction
WDT time-out
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
BOR, POR
POR
6-2. If clock
Setting Event
for
6.2
The Reset times for various types of device Reset are
summarized in
SYSRST, is released after the POR and PWRT delay
times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
Device Reset Times
POR, BOR
POR, BOR
PWRSAV instruction, POR, BOR
POR, BOR
POR, BOR
POR, BOR
POR
Table
6-3. The System Reset signal,
© 2011 Microchip Technology Inc.
Clearing Event
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