TDGL007 Microchip Technology, TDGL007 Datasheet - Page 85

• Manufacturer Part Number: TDGL007
• Description: Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
• Manufacturer: Microchip Technology

Specifications of TDGL007

• Product: Development Boards
• Interface Type: CAN, I2C
• Operating Supply Voltage: 5 V

TABLE 6-3:
© 2011 Microchip Technology Inc.
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
Reset Type
2:
3:
4:
5:
6:
T
T
Power-up Timer delay (if regulator is disabled). T
states, including waking from Sleep mode if the regulator is enabled.
T
T
oscillator clock to the system.
T
T
STARTUP
OST
RST
POR
LOCK
FSCM
= Internal state Reset time (20 μs nominal).
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
= Power-on Reset delay (10 μs nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time (20 μs nominal).
= Fail-Safe Clock Monitor delay (100 μs nominal).
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
Any Clock
Any Clock
Any Clock
Any Clock
Any Clock
= Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal
Clock Source
dsPIC33FJXXXMCX06A/X08A/X10A
T
T
T
T
POR
POR
POR
POR
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
+ T
+ T
+ T
+ T
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
STARTUP
RST
RST
RST
RST
+ T
+ T
+ T
+ T
RST
RST
RST
RST
is also applied to all returns from powered-down
System Clock
T
T
OST
OST
T
T
Delay
T
T
LOCK
LOCK
OST
+ T
OST
+ T
—
—
—
—
—
—
—
—
LOCK
LOCK
FSCM
T
T
T
T
T
T
Delay
FSCM
FSCM
FSCM
FSCM
FSCM
FSCM
—
—
—
—
—
—
—
—
DS70594C-page 85
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
3
3, 5, 6
3, 4, 6
3, 4, 5, 6
3
3
3
3
3
3
See Notes