TDGL007 Microchip Technology, TDGL007 Datasheet - Page 173

• Manufacturer Part Number: TDGL007
• Description: Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
• Manufacturer: Microchip Technology

Specifications of TDGL007

• Product: Development Boards
• Interface Type: CAN, I2C
• Operating Supply Voltage: 5 V

14.0
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The
support up to eight input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
FIGURE 14-1:
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the fea-
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
ICx Pin
dsPIC33FJXXXMCX06A/X08A/X10A
2: Some registers and associated bits
INPUT CAPTURE
tures of the dsPIC33FJXXXMCX06A/
X08A/X10A family of devices. How-
ever, it is not intended to be a compre-
hensive
complement the information in this data
sheet, refer to Section 12. “Input Cap-
ture” (DS70198) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Prescaler
(1, 4, 16)
Counter
3
INPUT CAPTURE BLOCK DIAGRAM
System Bus
ICxCON
reference
dsPIC33FJXXXMCX06A/X08A/X10A
ICM<2:0> (ICxCON<2:0>)
ICOV, ICBNE (ICxCON<4:3>)
Mode Select
Edge Detection Logic
source.
Clock Synchronizer
ICxI<1:0>
and
devices
To
in
(in IFSx Register)
Set Flag ICxIF
Interrupt
Logic
1.
2.
3.
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include the following:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Input capture can also be used to provide
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
additional sources of external interrupts
Note:
Simple Capture Event modes
- Capture timer value on every falling edge of
- Capture timer value on every rising edge of
Capture timer value on every edge (rising and
falling) of input at ICx pin
Prescaler Capture Event modes
- Capture timer value on every 4th rising
- Capture timer value on every 16th rising
4 buffer locations are filled
input at ICx pin
input at ICx pin
edge of input at ICx pin
edge of input at ICx pin
Logic
FIFO
R/W
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to ‘1’ (ICI<1:0> = 00).
From 16-Bit Timers
TMRy TMRz
1
ICxBUF
16
0
DS70594C-page 173
16
ICTMR
(ICxCON<7>)