TDGL007 Microchip Technology, TDGL007 Datasheet - Page 211

• Manufacturer Part Number: TDGL007
• Description: Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
• Manufacturer: Microchip Technology

Specifications of TDGL007

• Product: Development Boards
• Interface Type: CAN, I2C
• Operating Supply Voltage: 5 V

20.0
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC33FJXXXMCX06A/X08A/X10A
device family. The UART is a full-duplex, asynchronous
system that can communicate with peripheral devices,
such as personal computers, LIN/J2602, RS-232 and
RS-485 interfaces. The module also supports a hard-
ware flow control option with the UxCTS and UxRTS
pins and also includes an IrDA
FIGURE 20-1:
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the fea-
Note 1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as
2: Some registers and associated bits
2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e.,
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
tures of the dsPIC33FJXXXMCX06A/
X08A/X10A family of devices. How-
ever, it is not intended to be a compre-
hensive
complement the information in this data
sheet, refer to Section 17. “UART”
(DS70188) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
a DMA IRQ source, a DMA transfer occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as
a result of a UART1 or UART2 transmission or reception.
UTXISEL<1:0> = 00 and URXISEL<1:0> = 00).
UART SIMPLIFIED BLOCK DIAGRAM
reference
dsPIC33FJXXXMCX06A/X08A/X10A
®
Hardware Flow Control
encoder and decoder.
Baud Rate Generator
UART Transmitter
UART Receiver
source.
IrDA
®
To
in
The primary features of the UART module are:
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
• Fully Integrated Baud Rate Generator with 16-Bit
• Baud Rates Ranging from 10 Mbps to 38 bps at 40
• 4-Deep First-In-First-Out (FIFO) Transmit Data
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
• Transmit and Receive Interrupts
• A Separate Interrupt for all UART Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UART is shown in
Figure
important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
through the UxTX and UxRX Pins
UxRTS Pins
Prescaler
MIPS
Buffer
(9th bit = 1)
20-1. The UART module consists of these key
UxRTS/BCLK
UxCTS
UxRX
UxTX
DS70594C-page 211