TDGL007 Microchip Technology, TDGL007 Datasheet - Page 76

• Manufacturer Part Number: TDGL007
• Description: Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
• Manufacturer: Microchip Technology

Specifications of TDGL007

• Product: Development Boards
• Interface Type: CAN, I2C
• Operating Supply Voltage: 5 V

dsPIC33FJXXXMCX06A/X08A/X10A
5.2
The
program memory array is organized into rows of
64 instructions or 192 bytes. RTSP allows the user to
erase a page of memory at a time, which consists of
eight rows (512 instructions), and to program one row
or one word at a time.
and programming times. The 8-row erase pages and
single row write rows are edge-aligned, from the begin-
ning of program memory, on boundaries of 1536 bytes
and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers in sequential order. The
instruction words loaded must always be from a group
of 64 boundaries.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles), because only the buffers are
written.
programming each row.
5.3
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode.
programming operation is finished.
The programming time depends on the FRC accuracy
(see
Tuning register (see
formula to calculate the minimum and maximum values
for the row write time, page erase time and word write
cycle time parameters (see
EQUATION 5-1:
DS70594C-page 76
--------------------------------------------------------------------------------------------------------------------------- -
7.37 MHz
Table
dsPIC33FJXXXMCX06A/X08A/X10A
The
RTSP Operation
Programming Operations
A
26-19) and the value of the FRC Oscillator
×
programming
processor
(
FRC Accuracy
Register
Table 26-12
PROGRAMMING TIME
T
stalls
Table
cycle
)%
9-4). Use the following
×
26-12).
shows typical erase
(waits)
(
FRC Tuning
is
required
until
)%
Flash
the
for
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
Register
write time is equal to
EQUATION 5-2:
The maximum row write time is equal to
EQUATION 5-3:
Setting the WR bit (NVMCON<15>) starts the
operation and the WR bit is automatically cleared
when the operation is finished.
5.4
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 0x55 and 0xAA to the
NVMKEY register. Refer to
Operations”
T
T
RW
RW
=
=
----------------------------------------------------------------------------------------------- - 1.586ms
7.37 MHz
----------------------------------------------------------------------------------------------- - 1.435ms
7.37 MHz
9-4) are set to ‘b111111, the minimum row
Control Registers
for further details.
×
×
(
(
11064 Cycles
11064 Cycles
1 0.05
1
Equation
–
+
MINIMUM ROW WRITE
TIME
MAXIMUM ROW WRITE
TIME
© 2011 Microchip Technology Inc.
0.05
(Register
Section 5.3 “Programming
)
)
×
×
5-2.
(
(
1 0.00375
1 0.00375
–
–
5-1) controls which
Equation
)
)
=
=
5-3.